ATTINY13V-10PI Ver la hoja de datos (PDF) - Atmel Corporation
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ATTINY13V-10PI Datasheet PDF : 177 Pages
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SRAM Data Memory
Figure 9 shows how the ATtiny13 SRAM Memory is organized.
The lower 160 Data memory locations address both the Register File, the I/O memory
and the internal data SRAM. The first 32 locations address the Register File, the next 64
locations the standard I/O memory, and the last 64 locations address the internal data
SRAM.
The five different addressing modes for the Data memory cover: Direct, Indirect with
Displacement, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In
the Register File, registers R26 to R31 feature the indirect addressing pointer registers.
The direct addressing reaches the entire data space.
The Indirect with Displacement mode reaches 63 address locations from the base
address given by the Y- or Z-register.
When using register indirect addressing modes with automatic pre-decrement and post-
increment, the address registers X, Y, and Z are decremented or incremented.
The 32 general purpose working registers, 64 I/O Registers, and the 64 bytes of internal
data SRAM in the ATtiny13 are all accessible through all these addressing modes. The
Register File is described in “General Purpose Register File” on page 8.
Figure 9. Data Memory Map
Data Memory
32 Registers
64 I/O Registers
0x0000 - 0x001F
0x0020 - 0x005F
0x0060
Internal SRAM
(64 x 8)
0x009F
Data Memory Access Times
This section describes the general access timing concepts for internal memory access.
The internal data SRAM access is performed in two clkCPU cycles as described in Figure
10.
Figure 10. On-chip Data SRAM Access Cycles
T1
T2
T3
clk
CPU
Address
Data
WR
Data
RD
Compute Address
Address valid
Memory Access Instruction
Next Instruction
14 ATtiny13
2535G–AVR–01/07
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