ATMEGA406(2005) Ver la hoja de datos (PDF) - Atmel Corporation

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Fabricante

ATMEGA406
(Rev.:2005)

8-bit Microcontroller with 40K Bytes In-System Programmable Flash

Atmel Corporation 

resistors are activated. The Port D pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

Port D also serves the functions of various special features of the ATmega406 as listed in ”Alter-

nate Functions of Port D” on page 73.

2.2.12 SCL

SMBUS clock, Open Drain bidirectional pin.

2.2.13 SDA

SMBUS data, Open Drain bidirectional pin.

2.2.14 OC

High voltage output to drive Charge FET.

2.2.15 OD

High voltage output to drive Discharge FET.

2.2.16 OPC

High voltage output to drive Pre-charge FET.

2.2.17 NI

NI is the filtered negative input from the current sense resistor.

2.2.18 NNI

NNI is the unfiltered negative input from the current sense resistor.

2.2.19 PI

PI is the filtered positive input from the current sense resistor.

2.2.20 PPI

PPI is the unfiltered positive input from the current sense resistor.

2.2.21

NV/PV1/PV2/PV3/PV4

NV, PV1, PV2, PV3, and PV4 are the inputs for battery cells 1, 2, 3, and 4.

2.2.22 PVT

PVT is the sense input for deep under-voltage protection. This pin also defines the pull-up level

for the OD output.

2.2.23 BATT

Input for detecting when a charger is connected. This pin also defines the pull-up level for OC

and OPC outputs.

2.2.24 RESET

Reset input. A low level on this pin for longer than the minimum pulse length will generate a

reset, even if the clock is not running. The minimum pulse length is given in Table 11 on page

38. Shorter pulses are not guaranteed to generate a reset.

6 ATmega406

2548AS–AVR–01/05

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