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ATMEGA406(2005) Ver la hoja de datos (PDF) - Atmel Corporation

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ATMEGA406 Datasheet PDF : 19 Pages
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ATmega406
2.2 Pin Descriptions
2.2.1 VFET
Input to the internal voltage regulator.
2.2.2 VCC
Digital supply voltage. Normally connected to VREG.
2.2.3 VREG
Output from the internal voltage regulator.
2.2.4 VREF
Internal Voltage Reference for external decoupling.
2.2.5
VREFGND
Ground for decoupling of Internal Voltage Reference.
2.2.6 GND
Ground
2.2.7 SGND
Signal Ground.
2.2.8
Port A (PA7:PA0)
PA3:PA0 serves as the analog inputs to the Voltage A/D Converter.
Port A also serves as a low-voltage 8-bit bi-directional I/O port with internal pull-up resistors
(selected for each bit). As inputs, Port A pins that are externally pulled low will source current if
the pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes
active, even if the clock is not running.
Port A also serves the functions of various special features of the ATmega406 as listed in ”Alter-
nate Functions of Port A” on page 69.
2.2.9
Port B (PB7:PB0)
Port B is a low-voltage 8-bit bi-directional I/O port with internal pull-up resistors (selected for
each bit). As inputs, Port B pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port B pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port B also serves the functions of various special features of the ATmega406 as listed in ”Alter-
nate Functions of Port B” on page 71.
2.2.10
Port C (PC0)
Port C is a high voltage Open Drain output port.
2.2.11
Port D (PD1:PD0)
Port D is a low-voltage 2-bit bi-directional I/O port with internal pull-up resistors (selected for
each bit). As inputs, Port D pins that are externally pulled low will source current if the pull-up
5
2548AS–AVR–01/05

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