ATF1504BE Ver la hoja de datos (PDF) - Atmel Corporation

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ATF1504BE

High-performance CPLD

Atmel Corporation 

ATF1504BE

2.2 Schmitt Trigger

The Input Buffer of each input and I/O pin has an optional schmitt trigger setting. The schmitt

trigger option can be used to buffer inputs with slow rise times.

2.3 Output Drive Capability

Each output has a high/low drive option. The low drive option (slow slew rate) can be used to

reduce system noise by slowing down outputs that do not need to operate at maximum speed or

drive strength. Outputs default to high drive strength by Atmel software and can be set to low

drive strength through the slew rate option.

2.4 I/O Bank

The I/O pins of the ATF1504BE are grouped into two banks, Bank A and Bank B. Bank A com-

prises of I/O pins for macrocells 1 to 32 (Logic Block A and B), and it is powered by VCCIOA. Bank

B comprises of I/O pins for macrocells 33 to 64 (Logic Block C and D), and it is powered by

VCCIOB.

2.5 I/O Standard

The ATF1504BE supports a wide range of I/O standards which include LVTTL, LVCMOS33,

LVCMOS25, LVCMOS18 and LVCMOS15. The I/O pins of the ATF1504BE can also be individ-

ually configured to support SSTL-2 (Class I) and SSTL-3 (Class I) advanced I/O standards.

This and the two I/O banks, together, allow the ATF1504BE to be used for voltage level

translation.

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3637B–PLD–1/08

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