ATF1502AS-7AC44 Ver la hoja de datos (PDF) - Atmel Corporation
Número de pieza
componentes Descripción
Fabricante
ATF1502AS-7AC44 Datasheet PDF : 18 Pages
| |||
ATF1502AS
Power Down Mode
The ATF1502AS includes an optional pin controlled power
down feature.When this mode is enabled, the PD pin acts
as the power down pin. When the PD pin is high, the device
supply current is reduced to less than 3 mA. During power
down, all output data and internal logic states are latched
and held. Therefore, all registered and combinatorial output
data remain valid. Any outputs which were in a Hi-Z state at
the onset will remain at Hi-Z. During power down, all input
signals except the power down pin are blocked. Input and
I/O hold latches remain active to insure that pins do not
float to indeterminate levels, further reducing system
power. The power down pin feature is enabled in the logic
design file. Designs using the power down pin may not use
the PD pin logic array input. However, all other PD pin mac-
rocell resources may still be used, including the buried
feedback and foldback product term array inputs.
Power Down AC Characteristics(1)(2)
Symbol Parameter
tIVDH
tGVDH
tCVDH
tDHIX
tDHGX
tDHCX
tDLIV
tDLGV
tDLCV
tDLOV
Notes:
Valid I, I/O Before PD High
Valid OE(2) Before PD High
Valid Clock(2) Before PD High
I, I/O Don’t Care After PD High
OE(2) Don’t Care After PD High
Clock(2) Don’t Care After PD High
PD Low to Valid I, I/O
PD Low to Valid OE (Pin or Term)
PD Low to Valid Clock (Pin or Term)
PD Low to Valid Output
1. For slow slew outputs, add tSSO.
2. Pin or Product Term.
-7
Min Max
7
7
7
12
12
12
1
1
1
1
-10
Min Max
10
10
10
15
15
15
1
1
1
1
-15
Min Max
15
15
15
25
25
25
1
1
1
1
-20
Min Max
20
20
20
30
30
30
1
1
1
1
-25
Min Max
25
25
25
35
35
35
1
1
1
1
Units
ns
ns
ns
ns
ns
ns
µs
µs
µs
µs
11
Share Link: 