ATF1502ASV Ver la hoja de datos (PDF) - Atmel Corporation

Número de pieza

componentes Descripción

Fabricante

ATF1502ASV

High performance EEPROM CPLD

Atmel Corporation 

ATF1502ASV

order to support boundary-scan testing as described in detail by IEEE Standard 1149.1. A typi-

cal BSC consists of three capture registers or scan registers and up to two update registers.

There are two types of BSCs, one for input or I/O pin, and one for the macrocells. The BSCs in

the device are chained together through the capture registers. Input to the capture register chain

is fed in from the TDI pin while the output is directed to the TDO pin. Capture registers are used

to capture active device data signals, to shift data in and out of the device and to load data into

the update registers. Control signals are generated internally by the JTAG TAP controller. The

BSC configuration for the input and I/O pins and macrocells is shown below.

7.2 BSC Configuration for Input and I/O Pins (Except JTAG TAP Pins)

Figure 7-1. BSC Configuration for Input and I/O Pins (Except JTAG TAP Pins)

Dedicated

Input

To Internal

Logic

TDO

Capture

Registers

CLOCK

SHIFT

TDI

(From Next Register)

Note: The ATF1502ASV has a pull-up option on TMS and TDI pins. This feature is selected as a design

option.

9

1615J–PLD–01/06

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