ATF1502ASV Ver la hoja de datos (PDF) - Atmel Corporation

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ATF1502ASV

High performance EEPROM CPLD

Atmel Corporation 

Figure 1-3. Block Diagram

ATF1502ASV

B

32

1615J–PLD–01/06

Each of the 32 macrocells generates a buried feedback that goes to the global bus. Each input

and I/O pin also feeds into the global bus. The switch matrix in each logic block then selects 40

individual signals from the global bus. Each macrocell also generates a foldback logic term that

goes to a regional bus. Cascade logic between macrocells in the ATF1502ASV allows fast, effi-

cient generation of complex logic functions. The ATF1502ASV contains four such logic chains,

each capable of creating sum term logic with a fan-in of up to 40 product terms.

The ATF1502ASV macrocell, shown in Figure 1, is flexible enough to support highly complex

logic functions operating at high speed. The macrocell consists of five sections: product terms

and product term select multiplexer, OR/XOR/CASCADE logic, a flip-flop, output select and

enable, and logic array inputs.

Unused product terms are automatically disabled by the compiler to decrease power consump-

tion. A security fuse, when programmed, protects the contents of the ATF1502ASV. Two bytes

(16 bits) of User Signature are accessible to the user for purposes such as storing project name,

part number, revision or date. The User Signature is accessible regardless of the state of the

security fuse.

The ATF1502ASV device is an in-system programmable (ISP) device. It uses the industry stan-

dard 4-pin JTAG interface (IEEE Std. 1149.1), and is fully compliant with JTAG’s Boundary-scan

Description Language (BSDL). ISP allows the device to be programmed without removing it from

3

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