ATF1502AS Ver la hoja de datos (PDF) - Atmel Corporation

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ATF1502AS

High Performance E2PROM CPLD

Atmel Corporation 

ATF1502AS(L)

Design

Software

Support

All pin transitions are ignored until the PD pin is brought low. When the power-down feature is

enabled, the PD1 or PD2 pin cannot be used as a logic input or output. However, the pin’s

macrocell may still be used to generate buried foldback and cascade logic signals.

All power-down AC characteristic parameters are computed from external input or I/O pins,

with reduced-power bit turned on. For macrocells in reduced-power mode (reduced-power bit

turned on), the reduced-power adder, tRPA, must be added to the AC parameters, which

include the data paths tLAD, tLAC, tIC, tACL, tACH and tSEXP.

The ATF1502AS macrocell also has an option whereby the power can be reduced on a per-

macrocell basis. By enabling this power-down option, macrocells that are not used in an appli-

cation can be turned down, thereby reducing the overall power consumption of the device.

Each output also has individual slew rate control. This may be used to reduce system noise by

slowing down outputs that do not need to operate at maximum speed. Outputs default to slow

switching, and may be specified as fast switching in the design file.

ATF1502AS designs are supported by several third-party tools. Automated fitters allow logic

synthesis using a variety of high-level description languages and formats.

Power-up Reset

The ATF1502AS is designed with a power-up reset, a feature critical for state machine initial-

ization. At a point delayed slightly from VCC crossing VRST, all registers will be initialized, and

the state of each output will depend on the polarity of its buffer. However, due to the asynchro-

nous nature of reset and uncertainty of how VCC actually rises in the system, the following

conditions are required:

1. The VCC rise must be monotonic,

2. After reset occurs, all input and feedback setup times must be met before driving the

clock pin high, and,

3. The clock must remain stable during TD.

The ATF1502AS has two options for the hysteresis about the reset level, VRST, Small and

Large. During the fitting process users may configure the device with the Power-up Reset hys-

teresis set to Large or Small. Atmel POF2JED users may select the Large option by including

the flag “-power_reset” on the command line after “filename.POF”. To allow the registers to be

properly reinitialized with the Large hysteresis option selected, the following condition is

added:

4. If VCC falls below 2.0V, it must shut off completely before the device is turned on again.

When the Large hysteresis option is active, ICC is reduced by several hundred microamps as

well.

Security Fuse

Usage

A single fuse is provided to prevent unauthorized copying of the ATF1502AS fuse patterns.

Once programmed, fuse verify is inhibited. However, the 16-bit User Signature remains

accessible.

Programming

ATF1502AS devices are in-system programmable (ISP) devices utilizing the 4-pin JTAG pro-

tocol. This capability eliminates package handling normally required for programming and

facilitates rapid design iterations and field changes.

7

0995K–PLD–6/05

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