ATA6622C(2014) Ver la hoja de datos (PDF) - Atmel Corporation

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Fabricante

ATA6622C
(Rev.:2014)

LIN Bus Transceiver with 3.3V (5V) Regulator and Watchdog

Atmel Corporation 

3. Functional Description

3.1 Physical Layer Compatibility

Since the LIN physical layer is independent from higher LIN layers (e.g., the LIN protocol layer), all nodes with a LIN physical

layer according to revision 2.x can be mixed with LIN physical layer nodes, which, according to older versions (i.e., LIN 1.0,

LIN 1.1, LIN 1.2, LIN 1.3), are without any restrictions.

3.2 Supply Pin (VS)

The LIN operating voltage is VS = 5V to 27V. An undervoltage detection is implemented to disable data transmission if VS

falls below VSth < 4V in order to avoid false bus messages. After switching on VS, the IC starts in Fail-safe Mode, and the

voltage regulator is switched on.

The supply current is typically 10µA in Sleep Mode and 57µA in Silent Mode.

3.3 Ground Pin (GND)

The IC does not affect the LIN Bus in the event of GND disconnection. It is able to handle a ground shift up to 11.5% of VS.

The mandatory system ground is pin 5.

3.4 Voltage Regulator Output Pin (VCC)

The internal 3.3V/5V voltage regulator is capable of driving loads up to 85mA. It is able to supply the microcontroller and

other ICs on the PCB and is protected against overloads by means of current limitation and overtemperature shut-down.

Furthermore, the output voltage is monitored and will cause a reset signal at the NRES output pin if it drops below a defined

threshold Vthun. To boost up the maximum load current, an external NPN transistor may be used, with its base connected to

the VCC pin and its emitter connected to PVCC.

3.5 Voltage Regulator Sense Pin (PVCC)

The PVCC is the sense input pin of the 3.3V/5V voltage regulator. For normal applications (i.e., when only using the internal

output transistor), this pin is connected to the VCC pin. If an external boosting transistor is used, the PVCC pin must be

connected to the output of this transistor, i.e., its emitter terminal.

3.6 Bus Pin (LIN)

A low-side driver with internal current limitation and thermal shutdown and an internal pull-up resistor compliant with the LIN

2.x specification are implemented. The allowed voltage range is between –27V and +40V. Reverse currents from the LIN

bus to VS are suppressed, even in the event of GND shifts or battery disconnection. LIN receiver thresholds are compatible

with the LIN protocol specification. The fall time from recessive to dominant bus state and the rise time from dominant to

recessive bus state are slope controlled.

3.7 Input/Output Pin (TXD)

In Normal Mode the TXD pin is the microcontroller interface used to control the state of the LIN output. TXD must be pulled

to ground in order to have a low LIN-bus. If TXD is high or unconnected (internal pull-up resistor), the LIN output transistor is

turned off, and the bus is in recessive state. During Fail-safe Mode, this pin is used as output. It is current-limited to < 8mA.

and is latched to low if the last wake-up event was from pin WAKE or KL_15.

3.8 TXD Dominant Time-out Function

The TXD input has an internal pull-up resistor. An internal timer prevents the bus line from being driven permanently in

dominant state. If TXD is forced to low for longer than tDOM > 6ms, the LIN-bus driver is switched to recessive state.

To reactivate the LIN bus driver, switch TXD to high (> 10µs).

The time-out function is disabled in the ATA6626C. Switching to dominant level on the LIN bus occurs without any time

limitations.

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ATA6622C/ATA6624C/ATA6626C [DATASHEET]

4986O–AUTO–10/14

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