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AT90S8515

8-bit Microcontroller with 8K Bytes In-System Programmable Flash

Atmel Corporation 

• Bit 5 – SE: Sleep Enable

The SE bit must be set (one) to make the MCU enter the Sleep Mode when the SLEEP

instruction is executed. To avoid the MCU entering the Sleep Mode, unless it is the pro-

grammer’s purpose, it is recommended to set the Sleep Enable (SE) bit just before the

execution of the SLEEP instruction.

• Bit 4 – SM: Sleep Mode

This bit selects between the two available sleep modes. When SM is cleared (zero), Idle

Mode is selected as Sleep Mode. When SM is set (one), Power-down mode is selected

as Sleep Mode. For details, refer to the section “Sleep Modes”.

• Bits 3, 2 – ISC11, ISC10: Interrupt Sense Control 1, Bit 1 and Bit 0

The External Interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the

corresponding interrupt mask in the GIMSK are set. The level and edges on the external

INT1 pin that activate the interrupt are defined in Table 5.

Table 5. Interrupt 1 Sense Control

ISC11

ISC10 Description

0

0

The low level of INT1 generates an interrupt request.

0

1

Reserved

1

0

The falling edge of INT1 generates an interrupt request.

1

1

The rising edge of INT1 generates an interrupt request.

• Bits 1, 0 – ISC01, ISC00: Interrupt Sense Control 0, Bit 1 and Bit 0

The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the

corresponding interrupt mask are set. The level and edges on the external INT0 pin that

activate the interrupt are defined in Table 6.

Table 6. Interrupt 0 Sense Control

ISC01

ISC00 Description

0

0

The low level of INT0 generates an interrupt request.

0

1

Reserved

1

0

The falling edge of INT0 generates an interrupt request.

1

1

The rising edge of INT0 generates an interrupt request.

The value on the INTn pin is sampled before detecting edges. If edge interrupt is

selected, pulses with a duration longer than one CPU clock period will generate an inter-

rupt. Shorter pulses are not guaranteed to generate an interrupt. If low-level interrupt is

selected, the low level must be held until the completion of the currently executing

instruction to generate an interrupt. If enabled, a level-triggered interrupt will generate

an interrupt request as long as the pin is held low.

30 AT90S8515

0841G–09/01

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