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AT90S1200

8-Bit Microcontroller with 1K bytes In-System Programmable Flash

Atmel Corporation 

Architectural

Overview

AT90S1200

The fast-access register file concept contains 32 x 8-bit general purpose working regis-

ters with a single clock cycle access time. This means that during one single clock cycle,

one ALU (Arithmetic Logic Unit) operation is executed. Two operands are output from

the register file, the operation is executed, and the result is stored back in the register

file – in one clock cycle.

Figure 4. The AT90S1200 AVR RISC Architecture

0838H–AVR–03/02

The ALU supports arithmetic and logic functions between registers or between a con-

stant and a register. Single register operations are also executed in the ALU. Figure 4

shows the AT90S1200 AVR RISC microcontroller architecture. The AVR uses a Har-

vard architecture concept – with separate memories and buses for program and data

memories. The program memory is accessed with a 2-stage pipeline. While one instruc-

tion is being executed, the next instruction is pre-fetched from the program memory.

This concept enables instructions to be executed in every clock cycle. The program

memory is In-System Programmable Flash memory.

With the relative jump and relative call instructions, the whole 512 address space is

directly accessed. All AVR instructions have a single 16-bit word format, meaning that

every program memory address contains a single 16-bit instruction.

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