AT90S1200 Ver la hoja de datos (PDF) - Atmel Corporation
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AT90S1200 Datasheet PDF : 71 Pages
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MCU Control Register –
MCUCR
The MCU Control Register contains general microcontroller control bits for general MCU
control functions.
Bit
7
$35
–
Read/Write
R
Initial Value
0
6
5
4
3
–
SE
SM
–
R
R/W
R/W
R
0
0
0
0
2
1
0
–
ISC01 ISC00 MCUCR
R
R/W
R/W
0
0
0
• Bits 7, 6 – Res: Reserved Bits
These bits are reserved bits in the AT90S1200 and always read as zero.
• Bit 5 – SE: Sleep Enable
The SE bit must be set (one) to make the MCU enter the Sleep mode when the SLEEP
instruction is executed. To avoid the MCU entering the Sleep mode unless it is the pro-
grammers purpose, it is recommended to set the Sleep Enable SE bit just before the
execution of the SLEEP instruction.
• Bit 4 – SM: Sleep Mode
This bit selects between the two available sleep modes. When SM is cleared (zero), Idle
mode is selected as sleep mode. When SM is set (one), Power-down mode is selected
as sleep mode. For details, refer to the paragraph “Sleep Modes” on the following page.
• Bits 3, 2 – Res: Reserved Bits
These bits are reserved bits in the AT90S1200 and always read as zero.
• Bits 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0
The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the
corresponding interrupt mask in the GIMSK register is set. The level and edges on the
external INT0 pin that activate the interrupt are defined in Table 4.
Table 4. Interrupt 0 Sense Control
ISC01 ISC00 Description
0
0
The low level of INT0 generates an interrupt request.
0
1
Reserved
1
0
The falling edge of INT0 generates an interrupt request.
1
1
The rising edge of INT0 generates an interrupt request.
The value on the INT0 pin is sampled before detecting edges. If edge interrupt is
selected, pulses with a duration longer than one CPU clock period will generate an inter-
rupt. Shorter pulses are not guaranteed to generate an interrupt. If low level interrupt is
selected, the low level must be held until the completion of the currently executing
instruction to generate an interrupt. If enabled, a level triggered interrupt will generate an
interrupt request as long as the pin is held low.
18 AT90S1200
0838H–AVR–03/02
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