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AT90S1200 Ver la hoja de datos (PDF) - Atmel Corporation

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AT90S1200 Datasheet PDF : 71 Pages
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I/O Memory
The I/O space definition of the AT90S1200 is shown in the following table.
Table 1. The AT90S1200 I/O Space
Address Hex
Name Function
$3F
SREG Status REGister
$3B
GIMSK General Interrupt MaSK register
$39
TIMSK Timer/Counter Interrupt MaSK register
$38
TIFR
Timer/Counter Interrupt Flag register
$35
MCUCR MCU general Control Register
$33
TCCR0 Timer/Counter0 Control Register
$32
TCNT0 Timer/Counter0 (8-bit)
$21
WDTCR Watchdog Timer Control Register
$1E
EEAR EEPROM Address Register
$1D
EEDR EEPROM Data Register
$1C
EECR EEPROM Control Register
$18
PORTB Data Register, Port B
$17
DDRB Data Direction Register, Port B
$16
PINB
Input Pins, Port B
$12
PORTD Data Register, Port D
$11
DDRD Data Direction Register, Port D
$10
PIND
Input Pins, Port D
$08
ACSR Analog Comparator Control and Status Register
Note: Reserved and unused locations are not shown in the table.
All AT90S1200 I/Os and peripherals are placed in the I/O space. The different I/O loca-
tions are accessed by the IN and OUT instructions transferring data between the 32
general purpose working registers and the I/O space. I/O registers within the address
range $00 - $1F are directly bit-accessible using the SBI and CBI instructions. In these
registers, the value of single bits can be checked by using the SBIS and SBIC instruc-
tions. Refer to the instruction set chapter for more details.
For compatibility with future devices, reserved bits should be written to zero if accessed.
Reserved I/O memory addresses should never be written.
Some of the status flags are cleared by writing a logical one to them. Note that the CBI
and SBI instructions will operate on all bits in the I/O register, writing a one back into any
flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers
$00 to $1F only.
The different I/O and peripherals control registers are explained in the following
sections.
10 AT90S1200
0838HAVR03/02

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