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AT89S8253-24SC Ver la hoja de datos (PDF) - Atmel Corporation

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AT89S8253-24SC Datasheet PDF : 59 Pages
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The AT89S8253 provides the following standard features: 12K bytes of In-System Programma-
ble Flash, 2K bytes of EEPROM, 256 bytes of RAM, 32 I/O lines, programmable watchdog timer,
two data pointers, three 16-bit timer/counters, a six-vector, four-level interrupt architecture, a full
duplex serial port, on-chip oscillator, and clock circuitry. In addition, the AT89S8253 is designed
with static logic for operation down to zero frequency and supports two software selectable
power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters,
serial port, and interrupt system to continue functioning. The Power-down mode saves the RAM
contents but freezes the oscillator, disabling all other chip functions until the next external inter-
rupt or hardware reset.
The on-board Flash/EEPROM is accessible through the SPI serial interface. Holding RESET
active forces the SPI bus into a serial programming interface and allows the program memory to
be written to or read from, unless one or more lock bits have been activated.
2. Pin Configurations
2.1 40P6 – 40-lead PDIP
(T2) P1.0 1
(T2 EX) P1.1 2
P1.2 3
P1.3 4
(SS) P1.4 5
(MOSI) P1.5 6
(MISO) P1.6 7
(SCK) P1.7 8
RST 9
(RXD) P3.0 10
(TXD) P3.1 11
(INT0) P3.2 12
(INT1) P3.3 13
(T0) P3.4 14
(T1) P3.5 15
(WR) P3.6 16
(RD) P3.7 17
XTAL2 18
XTAL1 19
GND 20
40 VCC
39 P0.0 (AD0)
38 P0.1 (AD1)
37 P0.2 (AD2)
36 P0.3 (AD3)
35 P0.4 (AD4)
34 P0.5 (AD5)
33 P0.6 (AD6)
32 P0.7 (AD7)
31 EA/VPP
30 ALE/PROG
29 PSEN
28 P2.7 (A15)
27 P2.6 (A14)
26 P2.5 (A13)
25 P2.4 (A12)
24 P2.3 (A11)
23 P2.2 (A10)
22 P2.1 (A9)
21 P2.0 (A8)
2.2 44A – 44-lead TQFP
(MOSI) P1.5 1
(MISO) P1.6 2
(SCK) P1.7 3
RST 4
(RXD) P3.0 5
NC 6
(TXD) P3.1 7
(INT0) P3.2 8
(INT1) P3.3 9
(T0) P3.4 10
(T1) P3.5 11
33 P0.4 (AD4)
32 P0.5 (AD5)
31 P0.6 (AD6)
30 P0.7 (AD7)
29 EA/VPP
28 NC
27 ALE/PROG
26 PSEN
25 P2.7 (A15)
24 P2.6 (A14)
23 P2.5 (A13)
2 AT89S8253
3286H–MICRO–9/05

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