AT45DB161B Ver la hoja de datos (PDF) - Atmel Corporation
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AT45DB161B Datasheet PDF : 33 Pages
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AT45DB161B
Memory Architecture Diagram
SECTOR ARCHITECTURE
SECTOR 0 = 8 Pages
4,224 bytes (4K + 128)
SECTOR 1 = 248 Pages
130,944 bytes (124K + 3,968)
SECTOR 0
BLOCK ARCHITECTURE
BLOCK 0
BLOCK 1
SECTOR 2 = 256 Pages
135,168 bytes (128K + 4K)
SECTOR 3 = 256 Pages
135,168 bytes (128K + 4K)
BLOCK 30
BLOCK 31
BLOCK 32
BLOCK 33
BLOCK 62
BLOCK 63
BLOCK 64
BLOCK 65
BLOCK 66
8 Pages
PAGE ARCHITECTURE
PAGE 0
PAGE 1
PAGE 6
PAGE 7
PAGE 8
PAGE 9
PAGE 14
PAGE 15
PAGE 16
PAGE 17
PAGE 18
SECTOR 16 = 256 Pages
135,168 bytes (128K + 4K)
Device Operation
Read Commands
2224I–DFLSH–10/04
BLOCK 509
BLOCK 510
BLOCK 511
Block = 4224 bytes
(4K + 128)
PAGE 4093
PAGE 4094
PAGE 4095
Page = 528 bytes
(512 + 16)
The device operation is controlled by instructions from the host processor. The list of
instructions and their associated opcodes are contained in Tables 1 through 4. A valid
instruction starts with the falling edge of CS followed by the appropriate 8-bit opcode
and the desired buffer or main memory address location. While the CS pin is low, tog-
gling the SCK pin controls the loading of the opcode and the desired buffer or main
memory address location through the SI (serial input) pin. All instructions, addresses
and data are transferred with the most significant bit (MSB) first.
Buffer addressing is referenced in the datasheet using the terminology BFA9 - BFA0 to
denote the ten address bits required to designate a byte address within a buffer. Main
memory addressing is referenced using the terminology PA11 - PA0 and BA9 - BA0
where PA11 - PA0 denotes the 12 address bits required to designate a page address
and BA9 - BA0 denotes the ten address bits required to designate a byte address within
the page.
By specifying the appropriate opcode, data can be read from the main memory or from
either one of the two data buffers. The DataFlash supports two categories of read
modes in relation to the SCK signal. The differences between the modes are in respect
to the inactive state of the SCK signal as well as which clock cycle data will begin to be
output. The two categories, which are comprised of four modes total, are defined as
Inactive Clock Polarity Low or Inactive Clock Polarity High and SPI Mode 0 or SPI
Mode 3. A separate opcode (refer to Table 1 on page 10 for a complete list) is used to
select which category will be used for reading. Please refer to the “Detailed Bit-level
Read Timing” diagrams in this datasheet for details on the clock cycle sequences for
each mode.
CONTINUOUS ARRAY READ: By supplying an initial starting address for the main
memory array, the Continuous Array Read command can be utilized to sequentially
read a continuous stream of data from the device by simply providing a clock signal; no
additional addressing information or control signals need to be provided. The DataFlash
incorporates an internal address counter that will automatically increment on every clock
3
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