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AT40KAL

Military Reprogrammable FPGAs with FreeRAM™

Atmel Corporation 

RAM

4263B–AERO–06/03

AT40KAL

32 x 4 dual-ported RAM blocks are dispersed throughout the array as shown in Figure 7.

A 4-bit Input Data Bus connects to four horizontal local buses distributed over four sec-

tor rows (plane 1). A 4-bit Output Data Bus connects to four horizontal local buses dis-

tributed over four sector rows (plane 2). A 5-bit Input Address Bus connects to five

vertical express buses in same column. A 5-bit Output Address Bus connects to five ver-

tical express buses in same column. Ain (input address) and Aout (output address)

alternate positions in horizontally aligned RAM blocks. For the left-most RAM blocks,

Aout is on the left and Ain is on the right. For the right-most RAM blocks, Ain is on the

left and Aout is tied off, thus it can only be configured as a single port. For single-ported

RAM, Ain is the READ/WRITE address port and Din is the (bi-directional) data port.

Right-most RAM blocks can be used only for single-ported memories. WEN and OEN

connect to the vertical express buses in the same column.

Figure 7. RAM Connections (One Ram Block)

CLK

CLK

CLK

CLK

Din Dout

Ain

Aout

32 x 4 RAM

WEN

OEN CLK

Reading and writing of the 11 - 13 ns 32 x 4 dual-port FreeRAM are independent of

each other. Reading the 32 x 4 dual-port RAM is completely asynchronous. Latches are

transparent; when Load is logic 1, data flows through; when Load is logic 0, data is

latched. These latches are used to synchronize Write Adress, Write Enable Not, and Din

signals for a synchronous RAM. Each bit in the 32 x 4 dual-port RAM is also a transpar-

ent latch. The front-end latch and the memory latch together form an edge-triggered flip

flop. When a nibble (bit = 7) is (Write) addressed and LOAD is logic 1 and WE is logic 0,

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