AT25FS010 Ver la hoja de datos (PDF) - Atmel Corporation
Número de pieza
componentes Descripción
Fabricante
AT25FS010 Datasheet PDF : 24 Pages
| |||
locked-out sector/block and the corresponding status register control bits are shown in Table 4-5
on page 10.
The six bits, BP0, BP1, BP3, BP4 and WPEN, are nonvolatile cells that have the same proper-
ties and functions as the regular memory cells.
Table 4-5. Sector/Block Write Protect Bits
Level
Status Register Bits
BP4
BP3
BP1
BP0
locked Out
Locked-out
Blocks
0(none)
0
0
0
0
1(1/32)
0
1
0
0
2(1/16)
1
0
0
0
3(1/8)
1
1
0
0
4(1/4)
x
x
0
1
5(1/2)
x
x
1
0
6(ALL)
x
x
1
1
Array Address
AT25FS010
None
01F000H − 01FFFFH
01E000H − 01FFFFH
01C000H − 01FFFFH
018000H − 01FFFFH
010000H − 01FFFFH
000000H − 01FFFFH
None
Sector 8 of Block 4
Sector 7 − 8 of Block 4
Sector 5 − 8 of Block 4
ALL Sectors of Block 4
ALL Sectors of Block 3,4
ALL Sectors of ALL Blocks (1-4)
Note: 1. x = don’t care
The WRSR instruction also allows the user to enable or disable the Write Protect (WP) pin
through the use of the Write Protect Enable (WPEN) bit. Hardware write protection is enabled
when the WP pin is low and the WPEN bit is “1”. Hardware write protection is disabled when
either the WP pin is high or the WPEN bit is “0.” When the device is hardware write protected,
writes to the Status Register, including the Block Protect bits and the WPEN bit, and the locked-
out sectors in the memory array are disabled. Write is only allowed to sectors of the memory
which are not locked out. The WRSR instruction is self-timed to automatically erase and pro-
gram BP0, BP1, BP3, BP4 and WPEN bits. In order to write the status register, two separate
instructions must be executed. First, the device must be write enabled via the WREN instruction.
Then, CS must be low and the WRSR instruction and data for the six bits are entered. The
WRSR write cycle will begin once CS goes high. During the internal write cycle, all instructions
will be ignored except RDSR instructions. The AT25FS010 will automatically return to write dis-
able state at the completion of the WRSR cycle. The status register is factory programmed to all
0’s.
Note: When the WPEN bit is hardware write protected, it cannot be changed back to “0”, as long as the
WP pin is held low.
Table 4-6. WPEN Operation
WPEN WP WEN ProtectedBlocks
0
X
0
Protected
0
X
1
Protected
1
Low
0
Protected
1
Low
1
Protected
X
High
0
Protected
X
High
1
Protected
UnprotectedBlocks
Protected
Writable
Protected
Writable
Protected
Writable
Status Register
Protected
Writable
Protected
Protected
Protected
Writable
10 AT25FS010
5167E–SFLSH–5/09
Share Link: 