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NX25F641C-3T

64M-BIT SERIAL FLASH MEMORY WITH 4-PIN SPI INTERFACE

NexFlash -> Winbond Electronics 

NX25F641C

data may be beneficial to the timing of some high-speed

systems. The factory default setting is the falling edge of

SCK for standard SPI.

RCE=0 Read data is output on the falling edge of

SCK (Standard SPI).

RCE=1 Read data is output on the rising edge of

SCK(Fast SPI).

Table 2. Write Protect Range Sector Selection

Write Protect

Range Config. Bits

WR3 WR2 WR1 WR0

00 00

00 01

00 10

00 11

01 00

01 01

01 10

01 11

10 00

10 01

10 10

10 11

11 00

11 01

11 10

11 11

Write Protected Sectors (Hex)

WD=0

WD=1

None

None

0000-003F 3FC0-3FFF

0000-007F 3F80-3FFF

0000-00BF 3F40-3FFF

0000-00FF 3F00-3FFF

0000-013F 3EC0-3FFF

0000-017F 3E80-3FFF

0000-01BF 3E40-3FFF

0000-01FF 3E00-3FFF

0000-023F 3DC0-3FFF

0000-027F 3D80-3FFF

0000-02BF 3D40-3FFF

0000-02FF 3D00-3FFF

0000-033F 3CC0-3FFF

0000-037F 3C80-3FFF

ALL

ALL

HOLD-R/B, HR[1:0]

The Hold-Ready/Busy (HOLD-R/B) bits HR1 and HR0 are

located at bits CF[1:0] of the configuration register. These

two bits select one of four possible functions: No Connect,

HOLD input, R/B Output, or R/B Output with open drain.

The factory setting for the pin is “No Connect”.

HR1 HR0 Pin Configuration

0

0

HOLD input

0

1

No Connect

1

0

R/B Output (Open Drain)

1

1

R/B Output

Configured as a R/B output, the pin can serve as a

system interrupt. When R/B is high, the array is ready to

be programmed. When R/B is low, it is busy programming.

If configured with an open-drain, an external pull-up re-

sistor should be used.

As a HOLD input, the pin can be used in conjunction with

the CS and SCK pin to suspend a serial command

sequence without resetting the command. This can be

useful if a command is in process and a higher priority

task on the same SPI bus needs to be attended to. To

suspend a command, HOLD must be brought low while

CS and SCK are low. With HOLD low, further data on the

SI pin is ignored (even while SCK is clocked) and the SO

pin goes to or remains in a high-impedance state. To re-

sume the command sequence, HOLD must be brought

high when CS and SCK are low.

Status Register Bit Descriptions

The status register provides status of the Flash array’s

Ready/Busy condition (R/B), transfers between the SRAM

and program buffer (TR0 and TR1), Write-Enable/Disable

(WE), Compare Not Equal (CNE), Power Detect (PD) and

Data Integrity status (DI0 and DI1). The register can be

read using the Read Status Register command

(Figure 6).

Ready/Busy Status, BUSY

The BUSY status bit is located at bit ST[15] of the status

register. Testing the BUSY bit is one of several ways to

check Ready/Busy status of the array. At power-up the

BUSY bit is reset to 0.

BUSY=1 The device is busy programming.

BUSY=0 The deivce is ready for further use.

SRAM Transfer, TR0 and TR1

The TR status bits are located at bit ST[13] and ST[14] of

the status register. The bits provide status during the

Transfer Sector to SRAM, Transfer SRAM to SRAM, Com-

pare Sector to SRAM and Refresh Sector commands. An

active state 1 indicates the SRAM Array is not available

for use. The device will also indicate a BUSY state while

the TR bits are active. Upon power up the TR bits reset to

0.

TR=1 Transfer, Compare or Refresh in Process.

TR=0 Transfer, Compare or Refresh not in Process.

10

NexFlash Technologies, Inc.

PRELIMINARY NXSF032A-0502

05/06/02 ©

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