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AT25F512B-SSHT

512-Kilobit 2.7-volt Minimum SPI Serial Flash Memory

Atmel Corporation 

AT25F512B [Preliminary]

11.2

Write Status Register

The Write Status Register command is used to modify the BPL bit and the BP0 bit of the Status

Register. Before the Write Status Register command can be issued, the Write Enable command

must have been previously issued to set the WEL bit in the Status Register to a logical “1”.

To issue the Write Status Register command, the CS pin must first be asserted and the opcode

of 01h must be clocked into the device followed by one byte of data. The one byte of data con-

sists of the BPL bit value, four don’t care bits, the BP0 bit value, and two additional don’t care

bits (see Table 11-2). Any additional data bytes that are sent to the device will be ignored. When

the CS pin is deasserted, the BPL bit and the BP0 bit in the Status Register will be modified, and

the WEL bit in the Status Register will be reset back to a logical “0”. The value of BP0 and the

state of the BPL bit and the WP pin before the Write Status Register command was executed

(the prior state of the BPL bit and the state of the WP pin when the CS pin is deasserted) will

determine whether or not software protection will be changed. Please refer to Section 9.4 “Pro-

tected States and the Write Protect Pin” on page 13 for more details.

The complete one byte of data must be clocked into the device before the CS pin is deasserted,

and the CS pin must be deasserted on even byte boundaries (multiples of eight bits); otherwise,

the device will abort the operation, the state of the BPL and BP0 bits will not change, memory

protection status will not change, and the WEL bit in the Status Register will be reset back to the

logical “0” state.

If the WP pin is asserted, then the BPL bit can only be set to a logical “1”. If an attempt is made

to reset the BPL bit to a logical “0” while the WP pin is asserted, then the Write Status Register

Byte command will be ignored, and the WEL bit in the Status Register will be reset back to the

logical “0” state. In order to reset the BPL bit to a logical “0”, the WP pin must be deasserted.

Table 11-2.

Bit 7

BPL

Write Status Register Format

Bit 6

Bit 5

Bit 4

X

X

X

Bit 3

X

Bit 2

BP0

Bit 1

X

Bit 0

X

Figure 11-2. Write Status Register

CS

SCK

SI

SO

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

OPC ODE

STATUS REGISTER IN

0 0 0 0 0 0 0 1DXXXXDXX

MSB

MSB

HIGH-IMPEDANCE

19

3689C–DFLASH–12/08

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