AT25F512B-SSHT Ver la hoja de datos (PDF) - Atmel Corporation
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AT25F512B-SSHT Datasheet PDF : 34 Pages
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11.1.3 WPP Bit
The WPP bit can be read to determine if the WP pin has been asserted or not.
11.1.4 BP0 Bit
The BP0 bits provides feedback on the software protection status for the device. In addition, the
BP0 bit can also be modified to change the state of the software protection to allow the entire
memory array to be protected or unprotected. When the BP0 bit is in the logical “0” state, then
the entire memory array is unprotected. When the BP0 bit is in the logical “1” state, then the
entire memory array is protected against program and erase operations.
11.1.5 WEL Bit
The WEL bit indicates the current status of the internal Write Enable Latch. When the WEL bit is
in the logical “0” state, the device will not accept any Byte/Page Program, erase, Program OTP
Security Register, or Write Status Register commands. The WEL bit defaults to the logical “0”
state after a device power-up or reset operation. In addition, the WEL bit will be reset to the logi-
cal “0” state automatically under the following conditions:
• Write Disable operation completes successfully
• Write Status Register operation completes successfully or aborts
• Program OTP Security Register operation completes successfully or aborts
• Byte/Page Program operation completes successfully or aborts
• Block Erase operation completes successfully or aborts
• Chip Erase operation completes successfully or aborts
• Hold condition aborts
If the WEL bit is in the logical “1” state, it will not be reset to a logical “0” if an operation aborts
due to an incomplete or unrecognized opcode being clocked into the device before the CS pin is
deasserted. In order for the WEL bit to be reset when an operation aborts prematurely, the entire
opcode for a Byte/Page Program, erase, Program OTP Security Register, or Write Status Regis-
ter command must have been clocked into the device.
11.1.6
RDY/BSY Bit
The RDY/BSY bit is used to determine whether or not an internal operation, such as a program
or erase, is in progress. To poll the RDY/BSY bit to detect the completion of a program or erase
cycle, new Status Register data must be continually clocked out of the device until the state of
the RDY/BSY bit changes from a logical “1” to a logical “0”.
Figure 11-1. Read Status Register
CS
SCK
SI
SO
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
OPCODE
00000101
MSB
STATUS REGISTER
DATA
STATUS REGISTER
DATA
STATUS REGISTER
DATA
HIGH-IMPEDANCE
DDDDDDDDDDDDDDDDDDDDDDDD
MSB
MSB
MSB
18 AT25F512B [Preliminary]
3689C–DFLASH–12/08
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