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AT25080A Datasheet PDF : 20 Pages
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WRITE STATUS REGISTER (WRSR): The WRSR instruction allows the user to select
one of four levels of protection. The AT25080A/160A/320A/640A is divided into four
array segments. One-quarter, one-half, or all of the memory segments can be protected.
Any of the data within any selected segment will therefore be read only. The block write
protection levels and corresponding status register control bits are shown in Table 8.
Bits BP0, BP1, and WPEN are nonvolatile cells that have the same properties and func-
tions as the regular memory cells (e.g., WREN, tWC, RDSR).
Table 8. Block Write Protect Bits
Status
Register Bits
Level BP1
BP0
AT25080A
0
0
0
None
1 (1/4)
0
1
0300
− 03FF
2 (1/2)
1
0
0200
− 03FF
3 (All)
1
1
0000
− 03FF
Array Addresses Protected
AT25160A
AT25320A
None
None
0600
− 07FF
0C00
− 0FFF
0400
− 07FF
0800
− 0FFF
0000
− 07FF
0000
− 0FFF
AT25640A
None
1800
− 1FFF
1000
− 1FFF
0000
− 1FFF
The WRSR instruction also allows the user to enable or disable the write protect (WP)
pin through the use of the write protect enable (WPEN) bit. Hardware write protection is
enabled when the WP pin is low and the WPEN bit is “1”. Hardware write protection is
disabled when either the WP pin is high or the WPEN bit is “0”. When the device is hard-
ware write protected, writes to the status register, including the block protect bits and the
WPEN bit, and the block-protected sections in the memory array are disabled. Writes
are only allowed to sections of the memory that are not block-protected.
NOTE: When the WPEN bit is hardware write protected, it cannot be changed back to
“0” as long as the WP pin is held low.
Table 9. WPEN Operation
WPEN
0
0
1
1
X
X
WP
X
X
Low
Low
High
High
WEN
0
1
0
1
0
1
Protected
Blocks
Protected
Protected
Protected
Protected
Protected
Protected
Unprotected
Blocks
Protected
Writeable
Protected
Writeable
Protected
Writeable
Status
Register
Protected
Writeable
Protected
Protected
Protected
Writeable
8 AT25080A/160A/320A/640A
5082B–SEEPR–1/05
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