AT24C256C(2008) Ver la hoja de datos (PDF) - Atmel Corporation

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AT24C256C
(Rev.:2008)

Two-wire Serial EEPROM 256K (32,768 x 8)

Atmel Corporation 

AT24C256C

SOFTWARE RESET: After an interruption in protocol, power loss or system reset, any 2-wire part can be protocol reset

by following these steps:

a) Create a start bit condition,

b) Clock 9 cycles,

c) Create another start bit followed by stop bit condition as shown below.

The device is ready for next communication after above steps has been completed.

Figure 4. Software Reset

Start bit

Dummy Clock Cycles

Start bit

Stop bit

SCL

1

2

3

8

9

SDA

Figure 5. Bus Timing

SCL

SDA IN

tSU.STA

SDA OUT

tF

tLOW

tHD.STA

tHIGH

tHD.DAT

tLOW

tSU.DAT

tAA

tDH

Figure 6. Write Cycle Timing

SCL

tR

tSU.STO

tBUF

SDA

8th BIT

ACK

Note:

WORDn

STOP

CONDITION

(1)

twr

START

CONDITION

1. The write cycle time t is the time from a valid stop condition of a write sequence to the end of the

WR

internal clear/write cycle.

7

8568A–SEEPR–11/08

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