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AS8202NF Datasheet PDF : 20 Pages
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AS8202NF TTP-C2NF
Data Sheet - Detailed Description
Table 5. Host Interface Ports
Pin Name
OEB
READYB
INTB
RAM_CLK_TESTSE
USE_RAM_CLK
Mode
In
out (open drain)
out (open drain)
in
in
Width
1
1
1
1
1
Comment
CNI output enable, active low
CNI ready, active low
CNI interrupt, time signal, active low
HOST clock
HOST clock pin enable
Asynchronous READYB permits the shortest possible bus cycle but eventually requires signal synchronization in the
application. Connect USE_RAM_CLK to VSS to enable this mode of operation.
Synchronous READYB uses an external clock (usually the host processor’s bus clock) for synchronization of the
signal, eliminating external synchronization logic. Connect USE_RAM_CLK to VDD and RAM_CLK_TESTSE to the
host processor's bus clock to enable this mode of operation.
Note: Due to possible metastability occurrence, it is not recommended to be used in safety critical systems.
Table 6. Asynchronous DPRAM interface
Symbol
Parameter
Conditions
Min Typ Max Units
Tc
Controller Cycle Time
25
ns
1a
Input Valid to CEB, WEB
2a
(Setup Time)
A[11:0]
D[15:0]
5
ns
1b
CEB, WEB to Input Invalid
A[11:0]
3
2b
(Hold Time)
D[15:0]
4
ns
3
Input Rising to CEB, WEB
Falling
CEB, WEB, OEB
51
ns
4
CEB, WEB Rising to Input
Falling
CEB, WEB, OEB
51,2
ns
5
Write Access Time (CEB,
WEB to READYB)
min = 1 Tc, max = 4 Tc
25
100
ns
6
CEB, WEB de-asserted to
READYB de-asserted
9.4
ns
7a
Input Valid to CEB, OEB
(Setup Time)
A[11:0]
5
ns
7b
CEB, OEB to Input Invalid
(Hold Time)
A[11:0]
2
ns
8
Input Rising to CEB, OEB
Falling
CEB, WEB, OEB
51
ns
9
CEB, OEB Rising to Input
Falling
CEB, WEB, OEB
51
ns
10
Read Access Time (CEB,
OEB to READYB)
min = 1.5 Tc, max = 8 Tc
37.5
200
ns
11a
CEB, OEB asserted to
signal asserted
D[15:0]
4.0
8.4
ns
11b
CEB, OEB de-asserted to
D[15:0]
3.8
11c
signal de-asserted
READYB
8
ns
8.8
12
READYB, D skew
±2
ns
13
RAM_CLK_TESTSE
Rising to READYB Falling
USE_RAM_CLK=1
3.7
13.5 ns
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Revision 2.1
10 - 20
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