AS8202 Ver la hoja de datos (PDF) - austriamicrosystems AG
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AS8202 Datasheet PDF : 10 Pages
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TTP/C-C2 Communication Controller – Preliminary Data Sheet
AS8202
Reset and Oscillator
Pin Name
xin0
xout0
xin1
xout1
plloff
resetb
mode
in
out
in
out
in
in
width
1
1
1
1
1
1
Comment
main oscillator input
main oscillator output
bus guardian oscillator input
bus guardian oscillator output
PLL disable
external reset
Table 1: Reset and Oscillator Ports
External Reset Signal
To issue a reset of the chip the resetb port has to be driven low for at least
µs. After
power-up the reset must overlap the build-up time of the oscillator circuit.
Integrated Power-On Reset
The Device has an internal Power-On Reset generator. When supply voltage ramps up, the
internal reset signal is kept active (low) for about 33 µs typical.
Parameter
Symbol Min
supply voltage slope
dV/dt
250
power on reset active time after VDD > 1,0V tpon_res
25
Typ Max
-
-
33
49
Unit
kV/s
us
Oscillator circuitry
The internal oscillator cell requires an external quartz or an external oscillator respectively. The
frequency applied on the main clock input (xin0, xout0) can be reduced by a factor of four by
using the internal PLL. In order to generate an internal frequency of 40 MHz using the internal
PLL, an external quartz or quartz oscillator with a frequency of 10 MHz is connected and the
plloff input is tied low. The bus guardian clock has no internal PLL.
20MHz
16MHz
‚1‘
10MHz
16MHz
‚0‘
40MHz
16MHz
oscillator
oscillator
‚1‘
n.c.
n.c.
xout0 xin0
AS8202
xout1 xin1
20 MHz
xout0 xin0
AS8202
xout1 xin1
40 MHz
xout0 xin0
AS8202
xout1 xin1
40 MHz
Figure 3: Quartz Circuit PLL off Figure 4: Quartz Circuit PLL on
Figure 5: Oscillator Circuit
Rev. 1.0, October 2000
Page 8 of 8
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