AS1521-BTSU Ver la hoja de datos (PDF) - austriamicrosystems AG
Número de pieza
componentes Descripción
Fabricante
AS1521-BTSU
austriamicrosystems AG
AS1521-BTSU Datasheet PDF : 29 Pages
| |||
AS1520/AS1521
Data Sheet - Electrical Characteristics
1. Tested at VDD1 = VDD2 = VDD3 = +3V; COM = GND; bit RANGE (page 15) = 1, single-ended input mode.
2. Relative accuracy is the deviation of the analog value at any code from its theoretical value after the gain error
and offset error have been nulled.
3. Offset nulled.
4. Ground on channel; sinewave applied to all off channels.
5. Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty
cycle.
6. The absolute voltage range for the analog inputs (CH0:CH7, and COM) is from GND to VDD1.
7. External load should not change during conversion for specified accuracy. Guaranteed specification of 2mV/mA
is a result of production test limitations.
8. AS1520/AS1521 performance is limited by the device noise floor, typically 300µVp-p.
9. Electrical characteristics are guaranteed from VDD1(MIN) = VDD2(MIN) = VDD3(MIN) to VDD1(MAX) = VDD2(MAX) =
VDD3(MAX). For operations beyond this range, see Typical Operating Characteristics on page 11. For guaranteed
specifications beyond the limits, contact austriamicrosystems, AG.
10. AIN = mid-scale; bit RANGE (page 15) = 1; tested with 20pF on DOUT, 20pF on SSTRB, and fSCLK = 4.8MHz
@ GND to VDD2.
11. SCLK = DIN = GND, CSN = VDD2.
Timing Characteristics
Table 5. AS1520 Timing Characteristics – (Figures 3, 4, 21, 23; VDD1 = VDD2 = VDD3 = +4.5 to +5.5V; TAMB = TMIN to
TMAX (unless otherwise specified).
Symbol
Parameter
Conditions
Min Typ Max Units
tCP
SCLK Period
156
ns
tCH
SCLK Pulse Width High
62
ns
tCL
SCLK Pulse Width Low
62
ns
tDS
DIN to SCLK Setup
35
ns
tDH
DIN to SCLK Hold
0
ns
tCSS
CSN Fall to SCLK Rise Setup
35
ns
tCS0
SCLK Rise to CSN Fall Ignore
35
ns
tDOH
SCLK Rise to DOUT Hold
CLOAD = 20pF
10
20
ns
tSTH
SCLK Rise to SSTRB Hold
CLOAD = 20pF
10
20
ns
tSTV
SCLK Rise to DOUT Valid
CLOAD = 20pF
80
ns
tDOV
SCLK Rise to SSTRB Valid
CLOAD = 20pF
80
ns
tDOD
CSN Rise to DOUT Disable
CLOAD = 20pF
10
65
ns
tSTD
CSN Rise to SSTRB Disable
CLOAD = 20pF
10
65
ns
tDOE
CSN Fall to DOUT Enable
CLOAD = 20pF
65
ns
tSTE
CSN Fall to SSTRB Enable
CLOAD = 20pF
65
ns
tCSW
CSN Pulse Width High
100
ns
Table 6. AS1521 Timing Characteristics – (Figures 3, 4, 21, 23; VDD1 = VDD2 = VDD3 = +2.7 to +3.6V; TAMB = TMIN to
TMAX (unless otherwise specified).
Symbol
Parameter
Conditions
Min Typ Max Units
tCP
SCLK Period
208
ns
tCH
SCLK Pulse Width High
83
ns
tCL
SCLK Pulse Width Low
83
ns
tDS
DIN to SCLK Setup
45
ns
tDH
DIN to SCLK Hold
0
ns
tCSS
CSN Fall to SCLK Rise Setup
45
ns
tCS0
SCLK Rise to CSN Fall ignore
45
ns
www.austriamicrosystems.com
Revision 1.00
9 - 29
Share Link: