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AS1161

20MHz - 66MHz, 10-Bit Bus, IEEE 1149.1 (JTAG) Compliant LVDS Serializer/Deserializer

austriamicrosystems AG 

AS1160/AS1161

Datasheet - Pinout

4 Pinout

Pin Assignments and Descriptions

Figure 2. AS1160 Pin Assignments (Top View)

A1

A2

A3

A4

A5

A6

A7

DGND N/C DIN0 SYNC1 AVDD AVDD N/C

B1

DIN1

B2

B3

B4

B5

B6

B7

N/C SYNC2 AVDD AGND AGND AVDD

C1 C2 C3 C4 C5 C6 C7

DIN3 DGND DVDD DVDD N/C AGND PWDNN

D1 D2 D3 D4 D5 D6 D7

DIN5 DIN2 DIN4 N/C DO- DEN DO+

E1

E2

E3

E4

E5

E6

E7

DIN7 DIN6 TMS TCLK DVDD DGND AGND

F1

F2

F3

F4

F5

F6

F7

TDI DIN8 TCK DIN9 DGND N/C AGND

G1 G2 G3 G4 G5 G6 G7

TDO TRSTNTCKR/FN DGND AVDD N/C N/C

Table 1. AS1160 Pin Descriptions

Pin Number

See Figure 2

Pin Name

DIN0:DIN9

TCKR/FN

DO+

DO-

DEN

PWDNN

TCLK

SYNC1,

SYNC2

DVDD

DGND

AVDD

AGND

TDI

TDO

TMS

TCK

TRSTN

N/C

Description

Data Input. LVTTL levels inputs. Data on these pins are loaded into a 10-bit input

register.

Transmit Clock Rising/Falling Strobe Select. LVTTL level input. Selects TCLK

active edge for strobing of DINx data.

1 = Rising edge.

0 = Falling edge.

+ Serial Data Output. Non-inverting Bus LVDS differential output.

- Serial Data Output. Inverting Bus LVDS differential output.

Serial Data Output Enable. LVTTL level input. If DEN is set to logic low the Bus LVDS

outputs are in tri-state condition.

Powerdown. LVTTL level input. Driving this pin low shuts down the PLL, tri-states the

outputs and puts the device into low power sleep mode.

Transmit Clock. LVTTL level input. Input for 20MHz to 66MHz system clock.

Synchronization. LVTTL level input. Assertion of SYNC (high) for at least 5 clock

cycles to be transmit a synchronization signal (SYNCPAT) on the Bus LVDS serial

output. Synchronization symbols continue to be sent if SYNCx continues to be

asserted. SYNC1 and SYNC2 pins are combined through an OR gate.

+3.0V to +3.6V Digital Circuit Power Supply. This is the supply for all digital circuitry.

Digital Circuit Ground. GND reference point for the digital part of the AS1160.

+3.0V to +3.6V Analog Power Supply (PLL and Analog Circuits). AVDD and DVDD

should be at the same potential and must not be more than 0.3V apart even on

transient basis. Both supplys should be decoupled by a capacitor of typically 10nF.

Analog Ground (PLL and Analog Circuits).

IEEE 1149.1 Test Data Input

IEEE 1149.1 Test Data Output

IEEE 1149.1 Test Mode Select Input

IEEE 1149.1 Test Clock Input

IEEE 1149.1 Test Reset Input

No Connection. Leave open-circuit, do not connect these pins.

www.austriamicrosystems.com/Interfaces-LVDS/AS1160_61

Revision 1.01

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