AS1161 Ver la hoja de datos (PDF) - austriamicrosystems AG

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Fabricante

AS1161

20MHz - 66MHz, 10-Bit Bus, IEEE 1149.1 (JTAG) Compliant LVDS Serializer/Deserializer

austriamicrosystems AG 

AS1160/AS1161

Datasheet - Timing Diagrams

Figure 25. SYNC Timing Delays

REN

PWDNN

TCLK

SYNC1

or

SYNC2

DO+

DO-

tSPW

Data

TCLK

SYNC1

or

SYNC2

tSPW minimum timing met

DO+

DO-

SYNCPAT

SYNCPAT

SYNCPAT

11111 00000

SYNCPAT

Data

Figure 26. Serializer Delay

DIN

TCLK

DO+

DO-

DIN0:9 Symbol n

tTCP

tSD

DIN0:9 Symbol n + 1

DIN0:9 Symbol n + 2

Timing shown for TCKR/FN = high

Start

Bit

DOUT0:9 Symbol n - 1

Stop Start

Bit Bit

DOUT0:9 Symbol n

0 12

89

0 12

Stop Start

Bit Bit

DOUT0:9 Symbol n + 1

89

0 12

www.austriamicrosystems.com/Interfaces-LVDS/AS1160_61

Revision 1.01

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