AS1120 Ver la hoja de datos (PDF) - austriamicrosystems AG
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AS1120 Datasheet PDF : 13 Pages
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AS1120
Datasheet - Detailed Description
The selection of internal or external backplane signal (see Table 5) is initiated after RESETN is disabled – the first ris-
ing edge at pin OSC after RESETN is disabled will force pin BPLOUT to deliver the internally generated backplane sig-
nal. If there is no rising edge at pin OSC, BPLOUT will simply buffer the signal at pin BPLIN.
Table 5. Backplane Source Generation Selection
Mode
OSC Pin
BPLOUT
Internal
Running
fOSC/16
External
Tied Low
BPLIN
Note: The LCD should never be supplied with static signals. Verify that signals at pins BPLIN and BPLOUT are
always running while VDD is supplied; note that pin BPLOUT is stopped during a reset.
Internal Mode – R/C Oscillator Running (Generating the Backplane)
Connect external R/C components to pin OSC as shown in Figure 1 on page 1. When an external REXT and CEXT are
connected to pin OSC, a clock signal whose frequency is equal to fOSC divided by 16 will be present at pin BPLOUT.
Note: Internal mode requires that pin BPLIN be connected to pin BPLOUT.
The oscillation period is approximately tOSC = 1/fOSC = 0.69 x REXT x CEXT, and the error between the expected fre-
quency and the generated frequency increases as indicated in Table 6.
Table 6. Oscillator Error Rate
Expected Oscillator Frequency
Error
1 kHz
1%
10 kHz
5%
50 kHz
20%
100 kHz
40%
Figure 7. AS1120 Clock Circuit
11
BPLIN
43
VDD
15
OSC
D
Q
Oscillator
CLRN
fOSC/16
CLRN
SEL
A
B
12
BPLOUT
13
RESETN
AS1120
External Mode: R/C Oscillator Stopped (External Backplane)
Connect pin OSC to VSS in order to block the internal oscillator. In this external mode, an external backplane signal
should be presented at pin BPLIN, which will be regenerated and presented at pin BPLOUT.
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