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MT28F320A18FF-70T

FLASH MEMORY

Micron Technology 

PRELIMINARY

2 MEG x 16

1.8V ENHANCED+ BOOT BLOCK FLASH MEMORY

Table 5: Command Descriptions

CODE

10h

20h

DEVICE MODE

Alt. Program Setup

Erase Setup

40h Program Setup

50h Clear Status Register

60h Protection

Configuration Setup

70h Read Status Register

90h Read Protection

Configuration

Register

98h Read Query

B0h Program/Erase

Suspend

C0h Program Device

Protection Register

Lock Device

Protection Register

D0h Erase Confirm

Program/Erase

Resume

FFh Read Array

01h Lock Block

BUS

CYCLE

First

First

First

First

First

First

First

First

First

First

DESCRIPTION

Operates the same as a PROGRAM SETUP command.

Prepares the CSM for an ERASE CONFIRM command. If the next command is

not an ERASE CONFIRM command, the command will be ignored, and the

device will go to read status mode and wait for another command.

A two-cycle command: The first cycle prepares for a PROGRAM operation, the

second cycle latches addresses and data and initiates the WSM to execute the

program algorithm. The Flash device outputs status register data on the

falling edge of OE# or CE#, whichever occurs first.

The WSM can set the block lock status (SR1), VPP Status (SR3), program status

(SR4),and erase status (SR5) bits in the status register to “1,” but it cannot

clear them to “0.” Issuing this command clears those bits to “0.”

Prepares the CSM for changes to the block locking status. If the next

command is not BLOCK UNLOCK, BLOCK LOCK, or BLOCK LOCK DOWN, then

the CSM will set both the program and erase status register bits to indicate a

command sequence error.

Places the device into read status register mode. Reading the device will

output the contents of the status register for the addressed bank. The device

will automatically enter this mode for the addressed bank after a PROGRAM

or ERASE operation has been initiated.

Puts the device into the read protection configuration register mode so that

reading the device will output the manufacturer/device codes, block lock

status, protection register, or protection register lock.

Puts the device into the read query mode so that reading the device will

output common flash interface information.

Suspends the currently executing PROGRAM/ERASE operation. The status

register will indicate when the operation has been successfully suspended by

setting either the program suspend (SR2) or erase suspend (SR6) and the

WSM status bit (SR7) to a “1” (ready). The WSM will continue to idle in the

suspend state, regardless of the state of all input control pins except RP#,

which will immediately shut down the WSM and the remainder of the chip if

RP# is driven to VIL.

Writes a specific code into the device protection register.

First Locks the device protection register; data can no longer be changed.

Second

First

First

Second

If the previous command was an ERASE SETUP command, then the CSM will

close the address and data latches, and it will begin erasing the block

indicated on the address pins. During programming/erase, the device will

respond only to the READ STATUS REGISTER, PROGRAM/ERASE SUSPEND

commands and will output status register data on the falling edge of OE# or

CE#, whichever occurs last.

If a program or erase operation was previously suspended, this command will

resume the operation.

During the read array mode, array data will be output on the data bus.

If the previous command was PROTECTION CONFIGURATION SETUP, the CSM

will latch the address and lock the block indicated on the address bus.

2 Meg x 16, 1.8V Enhanced+ Boot Block Flash Memory

MT28F320A18_3.fm - Rev. 3, Pub. 9/2002

10

©2002, Micron Technology Inc.

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