APL5912-KAC-TR Ver la hoja de datos (PDF) - Anpec Electronics

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APL5912-KAC-TR

0.8V Reference Ultra Low Dropout Linear Regulator

Anpec Electronics 

APL5912

Functional Description (Cont.)

Output Voltage Regulation (Cont.)

high bandwidth and DC gain provides very fast transient

response and less load regulation. It compares the

reference with the feedback voltage and amplifies the

difference to drive the output NMOS which provides

load current from VIN to VOUT.

Current-Limit

The APL5912 monitors the current via the output

NMOS and limits the maximum current to prevent load

and APL5912 from damages during overload or short-

circuit conditions.

Under-Voltage Protection (UVP)

The APL5912 monitors the voltage on FB pin after soft-

start process is finished. Therefore the UVP is disable

during soft-start. When the voltage on FB pin falls below

the under-voltage threshold, the UVP circuit shuts off

the output immediately. After a while, the APL5912

starts a new soft-start to regulate output.

Thermal Shutdown

A thermal shutdown circuit limits the junction temperature

of APL5912. When the junction temperature exceeds

+150°C, a thermal sensor turns off the output NMOS,

allowing the device to cool down. The regulator regu-

lates the output again through initiation of a new soft-

start cycle after the junction temperature cools by

50oC, resulting in a pulsed output during continuous

thermal overload conditions. The thermal shutdown

designed with a 50oC hysteresis lowers the average

junction temperature during continuous thermal

overload conditions, extending life time of the device.

For normal operation, device power dissipation should

be externally limited so that junction temperatures will

not exceed +125°C.

Enable Control

The APL5912 has a dedicated enable pin (EN). A logic

low signal (VEN< 0.3V) applied to this pin shuts down

the output. Following a shutdown, a logic high signal

re-enables the output through initiation of a new

softstart cycle. Left open, this pin is pulled up by an

internal current source (10µA typical) to enable

operation. It’s not necessary to use an external transistor

to save cost.

Power-OK and Delay

The APL5912 indicates the status of the output voltage

by monitoring the feedback voltage (VFB) on FB pin.

As the VFB rises and reaches the rising Power-OK

threshold (VPOK), an internal delay function starts to

perform a delay time. At the end of the delay time, the

IC turns off the internal NMOS of the POK to indicate

the output is OK. As the VFB falls and reaches the

falling Power-OK threshold (VPNOK), the IC immediately

turns on the NMOS of the POK to indicate the output

is not OK without a delay time.

Application Information

Power Sequencing

The power sequencing of VIN and VCNTL is not necessary

to be concerned. But do not apply a voltage to VOUT

for a long time when the main voltage applied at VIN is

not present. The reason is the internal parasitic diode

from VOUT to VIN conducts and dissipates power

without protections due to the forward-voltage.

Output Capacitor

The APL5912 requires a proper output capacitor to

maintain stability and improve transient response over

temperature and current. The output capacitor selection

is to select proper ESR (equivalent series resistance)

and capacitance of the output capacitor for good stability

and load transient response.

Copyright © ANPEC Electronics Corp.

12

Rev. A.6 - Jun., 2005

www.anpec.com.tw

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