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MR27V3266D

2M x16 / 1M x32 Synchronous OTP ROM

Oki Electric Industry 

1 Semiconductor

MR27V3266D

PIN FUNCTION FOR SYNCHRONOUS READ OPERATION ( STO pin is low level or open )

PIN NAME

STO

FUNCTION

Static Operation

CLK

/CS

CKE

System Clock

Chip Select

Clock Enable

A0-A12

Address

/RAS

/CAS

/MR

DQ0-DQ31

DQM

/WORD

Row Address Strobe

Column Address Strobe

Mode Register Set

Data Output

Data Output Masking

x32/x16 Organization

Selection

VCC

VSS

VCCQ

VSSQ

NC

DC

Power Supply

Ground

Data Output Power Supply

Data Output Ground

No Connection

Don't Care

DESCRIPTION

Must be low for synchronous operation. Internal resistance

(around 10k ohms) pulls the input level down to VSS when

this pin is open. High level STO enables programming

operation compatible with standard OTPs.

All inputs are sampled at the rising edge.

Enables command sampling by the CLK signal with a low level

on the /CS input.

Masks internal system clock to freeze the CLK operation of

subsequent CLK cycle. CKE must be enabled for command

sampling cycles. CLK is disabled for two types of operations.

1)Clock Suspend

2)Power down.

Row and column addresses are multiplexed on the same pins.

Row address:RA0-RA12

Column address:CA0-CA6(x32) / CA0-CA7(x16)

Functionality depends on the combination.

See the function table.

Data outputs are valid at the rising edge of CLK for read

cycles. Except for read cycles DQn is high-Z state.

Data outputs are masked after two cycles from when high

level DQM is applied.

The /WORD pin defines the organization of each read

command to be x16 (word mode) or x32 (double word mode).

High=x32

Low=x16

3.3V Power supply

3.3V Power supply to DQ0-DQ31

Logical input level is ignored.

August , 1999

Revision 2.4

32M Synchronous OTP

4

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