MR27V3266D Ver la hoja de datos (PDF) - Oki Electric Industry

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MR27V3266D

2M x16 / 1M x32 Synchronous OTP ROM

Oki Electric Industry 

1 Semiconductor

READ OPERATIONS

MR27V3266D

CAS LATENCY

After sampling "Read" command MR27V3266D starts actual data read operation with sense amplifiers, and transmits

the data from sense amplifiers to data out buffers to start burst read. This flow of sequential functionality takes time

as clock cycles defined as CAS latency(CL). CAS latency is set in Mode Register as either four cycles or five cycles.

In this sequence(from sampling "Read" command to start of driving data bus) sense amplifiers consume maximum

current flow. The detailed sequence is below.

1. Fix column address of memory matrix driver. Row address is already fixed with "Row Active" command.

(at 1st cycle)

2. Read data of selected memory cells with sense amplifiers.

3. Deliver data detected with sense amplifiers to the register for data output latch.

4. Couple selectively the section of the register storing each (double)word to output buffers.

5. Turn off sense amplifiers to save power. (at CL-1 cycle)

6. Enable output buffers to drive data bus. (at CL-1 cycle)

7. Data output on data bus can be sampled at the rising edge of system clock at CL cycle.

New "Row Active" command or new "Read" command can be sampled to perform gapless burst read at CL-1 clock

cycle of the last "Read" command. New command preceding CL-1 cycle interrupts sense amplifiers to read the data at

the selected memory cells of the last "Read" command. Interrupted "Read" command perishes or outputs invalid data

before the starting of the data burst of new "Read" command. Refer to the timing chart of "Burst Read/Interrupt I" and

"Burst Read/Interrupt II".

BURST READ

Data outputs are consecutive during the cycle number defined as Burst Length(BL). The latest burst read is

completed unless any interruption such as "Precharge" command stops the sequential data output. Burst Length is set

in Mode Register as either four or eight. After sampling of "Read" command the first output can be read at the cycle

delayed by CAS latency. Burst Type is also stored in Mode register as either sequential or interleave. The output

buffers go into high impedance state after burst read sequence is finished, unless a new "Read" command has been

sampled to perform gapless read or preemptive read. Burst read can be interrupted by "Burst Stop" command or

"Precharge" command at the cycle delayed by CAS latency from the command. On condition that reading data with

sense amplifiers of preceding "Read" command is not interrupted by new "Read" command or "Row active" command,

burst read of preceding "Read" command is continued regularly until the burst data sequence of the new "Read"

command starts. The new(latest) burst data sequence always starts regularly.

DQM

Input level on DQM is sampled at rising edge of system clock to mask data at two cycles later. Output of masked data

is high-Z state.

August , 1999

Revision 2.4

32M Synchronous OTP

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