MSM7704-01 Ver la hoja de datos (PDF) - Oki Electric Industry

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componentes Descripción

Fabricante

MSM7704-01

2ch Single Rail CODEC

Oki Electric Industry 

¡ Semiconductor

MSM7704-01/02/03

DIN1

PCM signal input for channel 1 when the parallel mode is selected.

D/A conversion is performed with the serial PCM signal input to this pin, the RSYNC signal

synchronous with the serial PCM signal, and the BCLK signal, and then the analog output is

output from AOUT1 pin.

The data rate of the PCM signal is equal to the frequency of the BCLK signal.

The PCM signal is shifted at the falling edge of the BCLK signal and latched into the internal

register when shifted by eight bits.

The start of the PCM data (MSD) is identified at the rising edge of RSYNC.

When the serial mode is selected, this pin is not used and should be connected to GND (0 V).

DIN2

PCM signal input for channel 2 when the parallel mode is selected.

D/A conversion is performed with the serial PCM signal input to this pin, the RSYNC signal

synchronous with the serial PCM signal, and the BCLK signal, and then the analog output is

output from AOUT2 pin.

The data rate of the PCM signal is equal to the frequency of the BCLK signal.

The PCM signal is shifted at the falling edge of the BCLK signal and latched into the internal

register when shifted by eight bits.

The start of the PCM data (MSD) is identified at the rising edge of RSYNC.

When the serial mode is selected, this pin is used for the 2ch multiplexed PCM signal input.

BCLK

Shift clock signal input for the DIN1, DIN2, DOUT1, and DOUT2 signals.

The frequency, equal to the data rate, is 64, 96, 128, 192, 256, 384, 512, 768, 1024, 1536, 1544, 2048,

or 200 kHz. Setting this signal to logic "1" or "0" drives both transmit and receive circuits to the

power saving state.

RSYNC

Receive synchronizing signal input.

Eight bits PCM data required are selected from a series of PCM signal to the DIN1 and DIN2 pins

by the receive synchronizing signal.

All timing signals in the receive section are synchronized by this synchronizing signal. This

signal must be synchronized in phase with the BCLK (generated from the same clock source as

BCLK). The frequency should be 8 kHz ±50 ppm to guarantee the AC characteristics which are

mainly the frequency characteristics of the receive section.

However, unless the frequency characteristics of the system used are strictly specified, this

device can operate in the range of 6 kHz to 9 kHz, but the electrical characteristics specified in

the data sheet are not guaranteed.

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