L4972A Ver la hoja de datos (PDF) - STMicroelectronics

Número de pieza

componentes Descripción

Fabricante

L4972A

2A SWITCHING REGULATOR

STMicroelectronics 

L4972A

Table 2. Pin Description

N°

1

2

3

4

5, 6 15,

16

7

8

9

10

11

12, 19

13

14

17

18

20

Pin

BOOTSTRAP

RESET DELAY

RESET OUT

RESET INPUT

GROUND

Function

A Cboot capacitor connected between this terminal and the output allows to drive

properly the internal D-MOS transistor.

A Cd capacitor connected between this terminal and ground determines the reset

signal delay time.

Open Collector Reset/power Failand the output voltages are safe. Signal Output.

This output is high when the supply

Input of Power Fail Circuit. The threshold is 5.1V. It may be connected via a divider

to the input for power fail function. It must be connected to the pin 14 an external

30KΩ resistor when power fail signal not required.

Common Ground Terminal

FREQUENCY

COMPENSATION

SOFT START

FEEDBACK INPUT

SYNC INPUT

SUPPLY VOLTAGE

N.C.

Vref

Vstart

OSCILLATOR

OSCILLATOR

OUTPUT

A series RC network connected between this terminal and ground determines the

regulation loop gain characteristics.

Soft Start Time Constant. A capacitor is connected between the sterminal and

ground to define the soft start time constant.

The Feedback Terminal of the Regulation Loop. The output is connected directly to

this terminal for 5.1V operation; It is connected via a divider for higher voltages.

Multiple L4972A’s are synchronized by connecting pin 10 inputs together or via an

external syncr. pulse.

Unregulated Input Voltage.

Not Connected.

5.1V Vref Device Reference Voltage.

Internal Start-up Circuit to Drive the Power Stage.

Rosc. External resistor connected to ground determines the constant charging

current of Cosc.

Cosc. External capacitor connected to ground determines (with Rosc) the switching

frequency.

Regulator Output.

Figure 3. Pin Connection (Top view)

BOOTSTRAP

RESET DELAY

RESET OUT

P. FAIL INPUT

GND

GND

FREQ. COMP.

SOFT START

FEEDBACK IN.

SYNC INPUT

1

20

2

19

3

18

4

17

5

16

6

15

7

14

8

13

9

12

10

11

DIP20

OUTPUT

N.C.

C OSC

R OSC

GND

GND

Vstart

Vref

N.C.

Vi

2/22

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