FAN6550 Ver la hoja de datos (PDF) - Fairchild Semiconductor
Número de pieza
componentes Descripción
Fabricante
FAN6550 Datasheet PDF : 12 Pages
| |||
FAN6550
2A DDR Bus Termination Regulator
www.fairchildsemi.com
Features
• Can source and sink up to 2A continous, 3A peak
• No heatsink required
• Integrated Power MOSFETs
• Generates termination voltages for DDR SDRAM
• VREF input available for external voltage divider
• Separate voltages for VCCQ and PVDD
• Buffered VREF output
• VOUT of ±3% or less at 2A
• Minimum external components
• 0°C to 70°C operating range
• Shutdown for standby or suspend mode operation
• Thermal Shutdown ≈ 130ºC
Block Diagram
Description
The FAN6550 switching regulator is designed to convert
voltage supplies ranging from 2.3V to 4V into a desired out-
put voltage or termination voltage for DDR SDRAM mem-
ory. The FAN6550 can be implemented to produce regulated
output voltages in two different modes. In the default mode,
when the VREF pin is open, the FAN6550 output voltage is
50% of the voltage applied to VCCQ. The FAN6550 can also
be used to produce various user-defined voltages by forcing a
voltage on the VREFIN pin. In this case, the output voltage
follows the input VREFIN voltage. The switching regulator
is capable of sourcing or sinking up to 2A of current while
regulating an output VTT voltage to within 3% or less.
Transient output currents of ±3A can also be accommodated.
The FAN6550 can also be used in conjunction with series
termination resisitors to provide an excellent voltage source
for active termination schemes of high speed transmission
lines as those seen in high speed memory buses and distrib-
uted backplane designs.
15
16
14
VCCQ AVCC VREFOUT
200kΩ
VREFIN
11
200kΩ
AGND
13
–
+
VREF BUFFER
OSCILLATOR/
RAMP
GENERATOR
ERROR AMP
+
–
VFB
10
1
VDD
9
VDD
12
SHDN
2
7
PVDD1 PVDD2
VL1
(VOUT)
3
SQ
–
RQ
+
RAMP
COMPARATOR
6
VL2
(VOUT)
DGND
8
PGND1 PGND2
4
5
REV. 1.0.2 3/11/02
Share Link: 