AN1672D Ver la hoja de datos (PDF) - ON Semiconductor
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AN1672D Datasheet PDF : 10 Pages
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AN1672/D
translation would then be LVPECL to LVNECL Translation,
still using the LVEL91.
If a −5 V supply is available, signals may be translated to
NECL (see next segment) then ported to any LVNECL input.
From TTL to NECL
Several devices are available to accomplish TTL to NECL
translation in a single package: the −H424, −H124, and the
ELT24. Alternatively, translation from TTL to NECL could
be done in two stages: first TTL to PECL (ELT20 or ELT22),
second by passing though a PECL to NECL Translation
(EL91). The NECL or LVNECL output levels could then be
ported to any NECL or LVNECL receiver, since the levels
are the same. No power supply sequencing is needed, but all
supply connections are required for proper operation.
H424 as TTL to NECL
An “open”, floating TTL input will drift to near VCC and
considerations and may inject noise into the device under
this condition. It is recommended to tie any unused TTL
input to VCC.
H124 as TTL to NECL
Although no supply sequencing is required, if the VEE and
GND are powered up prior to the VCC connected, about 5 to
10 mA may be drawn from a “off” VCC supply. This could
draw the off VCC supply to −0.25 V, depending in the internal
“off” impedance.
H600 as TTL to NECL
This device boasts a 9 bit wide capability with a
bandwidth from <1 Hz (with sufficiently sharp edges) to
250 MHz. The ECL Enable input has an internal 50 kW
pulldown resistor to force an input default (LOW) state
when floating open. When both the TTL and ECL Enable
pins are forced LOW, the outputs will default to LOW.
H602 as TTL to NECL
This device has similarities to the −H600 with pulldown
resistors on the ENECL, LEN, and MR inputs.
ELT24 as TTL to NECL
Use the MC100EPT24D with a VEE “stand−off” resistor
of about 61 W to drop the 1.7 V difference between VEE of
LVPECL and PECL (mean IEE = 28 mA, sigma = 0.2 mA).
This reduces the operating voltage across the device from
5.0 V VEE supply to 3.3 V.
This device does not have an internal input resistor
network to force a default level on an open, floating input
pin. If floated open, the TTL input, Pin 2, will drift to near
VCC and may inject noise into the device. A 10 kW pullup
resistor may be connected from Pin 2 to VCC forcing a
default state (Q HIGH) under open or floating input
conditions.
From LVTTL/LVCMOS to PECL
Translation from LVTTL to PECL may be done in a single
device such as the H351, H606, ELT20, ELT22, or through
half of the ELT28.
For higher frequency operation, translation is done in two
stages:
1. LVTTL to LVPECL using EPT20, EPT22,
LVELT22, or EPT24
2. LVPECL signals into any PECL line receiver with
a VIHCMRmin able to recognize a LVPECL HIGH
level (such as EL17, EL14, EL13, etc.).
From LVTTL/LVCMOS to LVPECL
Use EPT20, EPT22, or LVELT22 to translate from
LVTTL/LVCMOS to LVPECL
From LVTTL to LVNECL
Use the MC100EPT24D
From LVTTL to NECL
Translation from LVTTL/LVCMOS to NECL is done in two
stages:
1. Use LVTTL/LVCMOS to LVPECL (EPT20,
EPT22, LVELT22)
2. Then use LVPECL to NECL (EL91).
From CMOS to PECL
The MC10H352 offers inputs with proper CMOS detect
levels for translating 5.0 V CMOS signals to PECL levels.
Non CMOS detect level devices may be used such as
ELT20, ELT22, and ELT28 for expended frequency range
with some small loss in duty cycle.
From CMOS to LVPECL
Translation from CMOS to LVPECL is done in two stages:
1. CMOS to PECL using a MC10H352 (or similar)
2. Then use a PECL to LVPECL translator,
MC100LVEL92.
From CMOS to LVNECL
Translation from CMOS to LVNECL is done in two stages:
1. CMOS to PECL using a MC10H352 (or similar)
2. Then use PECL to LVNECL via MC100LVEL91.
From CMOS to NECL
Translation from CMOS to NECL is done in two stages:
1. CMOS to PECL using a MC10H352 (or similar);
2. Then use PECL to NECL translator, MC100EL91.
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