AN-9048 Ver la hoja de datos (PDF) - Fairchild Semiconductor
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AN-9048 Datasheet PDF : 9 Pages
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assembly. Due to the importance of the stencil
design, many stencil types were tried to determine
the optimal stencil design for the recommended
footprint pad, on a typical application board with
Organic Surface Protectant (OSP) surface finish,
thermal vias, on FR-4. It was found through
statistical analysis the optimum solder paste
coverage for the center drain and IC pads was 50-
70% coverage using a 4 mil thick stencil.
(Dimensioned drawings of these stencil apertures
can be found in the appendix.) To allow gases to
escape during reflow it is recommended that the
paste be deposited in a grid allowing “channels”
for gases to vent. Various other stencil apertures
can be used, such as circles, but were not studied
here. The paste is printed on the outer pins with a
slightly reduced ratio to the PWB pad. IPC-7525
“Stencil Design Guidelines” gives a formula for
calculating the area ratio for paste release
prediction:
Area Ratio =
Area of Pad
L *W
=
Area of Aperture Walls 2 * (L *W ) * T
Where L is the length, W the width, and T the
thickness of the stencil. When using this equation,
an Area Ratio >0.66 should yield acceptable paste
release. The recommended stencil apertures can
be found in the appendix.
SOLDER PASTE
The 6x6 DrMOS is a RoHS compliant and lead
free package. The lead finish is NiPdAu. Any
standard lead free no clean solder paste commonly
used in the industry should work with this package.
The IPC Solder Products Value Council has
recommended that the lead free alloy, 96.5
Sn/3.0Au/0.5Cu, commonly known as SAC 305,
is “…the lead free solder paste alloy of choice for
the electronics industry”. Type 3 no-clean paste,
SAC 305 alloy, was used for the construction of
the boards studied to optimize the process.
Figure 4: Printed Solder Paste.
REFLOW PROFILE
The optimum reflow profile used for every
product and oven is different. Even the same
brand and model oven in a different facility may
require a different profile. The proper ramp and
soak rates are determined by the solder paste
vendor for their products. Obtaining this
information from the paste vendor is highly
recommended. If one is using a KIC® profiler,
downloading the latest paste library from KIC®
will yield ramp rate and soak times at temperature
for most commonly used solder pastes. The
Fairchild 6x6 DrMOS is rated for 260ºC peak
temperature reflow. Attached in the appendix is a
reflow profile example. This profile is provided
for reference only; different PWBs, ovens and
pastes will change this profile, perhaps dramatically.
VOIDING
Voiding is a very controversial topic in the
industry currently. The move to lead free solders,
due to various governmental regulations, has
created intense study in the area of solders, solder
joints and reliability effects. There are varying
viewpoints on the effect of vias and allowable
quantity. There are several types of voids
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