VT73127/DW Ver la hoja de datos (PDF) - Vaishali Semiconductor
Número de pieza
componentes Descripción
Fabricante
VT73127/DW Datasheet PDF : 4 Pages
| |||
VT73127
Preliminary
Figure 2. Pad Configuration
VT73127/D
X1
1
VDD1 2
X2
9
8 GND
VIN
GND
3
7
5
4
6
CLK
VDD2
OE
Table 1. Pad Description
Name
X1
VDD1
VIN
GND
Pad
1
2
3
4
Type
Xi
P
I
P
Description
Crystal connection. Connect to a 27 MHz pullable crystal
Core VDD. Connect to 3.3V
Tuning control input. Zero to 3.3V signal controls the frequency of the VCXO.
Connect to ground.
CLK
5
O Clock output
OE
6
I
Active HIGH output enable. When LOW, the output is held in a tri-state condition
VDD2
7
P
Output buffer VDD . Connect to 3.3V
GND
8
P Connect to ground.
X2
9
Xi Crystal connection. Connect to a 27 MHz pullable crystal.
Legend: I = Input
O = Output
P = Power supply connection
Xi = Crystal connections.
Table 2. Absolute Maximum Ratings
Parameter
Supply voltage, VDD
Conditions
Referenced to GND
Min Typ
Max
Units
7
V
Inputs and Clock Outputs
Referenced to GND -0.5
VDD+0.5 V
Soldering Temperature
Max of 10 seconds
260
°C
Storage temperature
-65
150
°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These
ratings are stress specifications only and correct functional operation of the device at these or any other conditions
above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
Table 3. Operating Conditions
Parameter
Operating Voltage, VDD
Input High Voltage, VIH, X1 pin only
Input Low Voltage, VIL, X1 pin only
Operating Temperature
Input crystal accuracy
Conditions
Min
3.0
2.5
0
Typ
3.3
Max
3.6
0.4
70
±30
Units
V
V
V
°C
ppm
2001-08-06
Page 2
MDST-0012-02
www.vaishali.com
Vaishali Semiconductor 747 Camden Avenue, Suite C Campbell CA 95008 Ph. 408.377.6060 Fax 408.377.6063
Share Link: 