DS1820S Ver la hoja de datos (PDF) - Dallas Semiconductor -> Maxim Integrated
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DS1820S Datasheet PDF : 27 Pages
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DS1820
The data obtained from the two reads of the 3–step
routine have the following interpretations:
00 There are still devices attached which have
conflicting bits in this position.
01 All devices still coupled have a 0–bit in this
bit position.
10 All devices still coupled have a 1–bit in this
bit position.
11 There are no devices attached to the 1–Wire
bus.
4. The bus master writes a 0. This deselects ROM2
and ROM3 for the remainder of this search pass,
leaving only ROM1 and ROM4 connected to the
1–Wire bus.
5. The bus master performs two more reads and
receives a 0–bit followed by a 1–bit. This indicates
that all devices still coupled to the bus have 0’s as
their second ROM data bit.
6. The bus master then writes a 0 to keep both ROM1
and ROM4 coupled.
7. The bus master executes two reads and receives
two 0–bits. This indicates that both 1–bits and 0–bits
exist as the third bit of the ROM data of the attached
devices.
8. The bus master writes a 0–bit. This deselects ROM1
leaving ROM4 as the only device still connected.
9. The bus master reads the remainder of the ROM bits
for ROM4 and continues to access the part if
desired. This completes the first pass and uniquely
identifies one part on the 1–Wire bus.
10. The bus master starts a new ROM search sequence
by repeating steps 1 through 7.
11. The bus master writes a 1–bit. This decouples
ROM4, leaving only ROM1 still coupled.
12. The bus master reads the remainder of the ROM bits
for ROM1 and communicates to the underlying logic
if desired. This completes the second ROM search
pass, in which another of the ROMs was found.
13. The bus master starts a new ROM search by repeat-
ing steps 1 through 3.
14. The bus master writes a 1–bit. This deselects
ROM1 and ROM4 for the remainder of this search
pass, leaving only ROM2 and ROM3 coupled to the
system.
15. The bus master executes two read time slots and
receives two zeros.
16. The bus master writes a 0–bit. This decouples
ROM3, and leaving only ROM2.
17. The bus master reads the remainder of the ROM bits
for ROM2 and communicates to the underlying logic
if desired. This completes the third ROM search
pass, in which another of the ROMs was found.
18. The bus master starts a new ROM search by repeat-
ing steps 13 through 15.
19. The bus master writes a 1–bit. This decouples
ROM2, leaving only ROM3.
20. The bus master reads the remainder of the ROM bits
for ROM3 and communicates to the underlying logic
if desired. This completes the fourth ROM search
pass, in which another of the ROMs was found.
Note the following:
The bus master learns the unique ID number (ROM data
pattern) of one 1–Wire device on each ROM Search
operation. The time required to derive the part’s unique
ROM code is:
960 µs + (8 + 3 x 64) 61 µs = 13.16 ms
The bus master is therefore capable of identifying 75 dif-
ferent 1–Wire devices per second.
I/O SIGNALING
The DS1820 requires strict protocols to insure data
integrity. The protocol consists of several types of
signaling on one line: reset pulse, presence pulse, write
0, write 1, read 0, and read 1. All of these signals, with
the exception of the presence pulse, are initiated by the
bus master.
The initialization sequence required to begin any com-
munication with the DS1820 is shown in Figure 11. A
reset pulse followed by a presence pulse indicates the
DS1820 is ready to send or receive data given the cor-
rect ROM command and memory function command.
The bus master transmits (TX) a reset pulse (a low sig-
nal for a minimum of 480 µs). The bus master then
releases the line and goes into a receive mode (RX).
The 1–Wire bus is pulled to a high state via the 5K
pull–up resistor . After detecting the rising edge on the
030598 11/27
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