AM29LV008T-120FC Ver la hoja de datos (PDF) - Advanced Micro Devices

Número de pieza

componentes Descripción

Fabricante

AM29LV008T-120FC

8 Megabit (1,048,576 x 8-Bit) CMOS 3.0 Volt-only, Sectored Flash Memory

Advanced Micro Devices 

PRELIMINARY

USER BUS OPERATIONS

Read Mode

The Am29LV008 has three control functions which

must be satisfied in order to obtain data at the outputs:

s CE is the power control and should be used for de-

vice selection (CE = VIL)

s OE is the output control and should be used to gate

data to the output pins if the device is selected

(OE = VIL)

s WE remains at VIH

Address access time (TACC) is equal to the delay from

stable addresses to valid output data. The chip enable

access time (TCE) is the delay from stable addresses

and stable CE to valid data at the output pins. The out-

put enable access time (TOE) is the delay from the fall-

ing edge of OE to valid data at the output pins

(assuming the addresses have been stable at least

TACC – TOE time).

Standby Mode

The Am29LV008 is designed to accommodate low

standby power consumption by applying the following

voltages to the CE and RESET pins: ICC3 for CMOS

compatible I/Os (current consumption <5 µA max.) is

enabled when a CMOS logic level ‘1’ (VCC ± 0.3 V) is

applied to the CE control pin with RESET = VCC ± 0.3

V. While in the ICC3 standby mode, the data I/O pins re-

main in the high impedance state independent of the

voltage level applied to the OE input. See the DC Char-

acteristics section for more details on Standby Modes.

Deselecting CE (CE and RESET = VCC ± 0.3 V) puts

the device into the ICC3 standby mode. If the device is

deselected during an Embedded Algorithm operation,

it continues to draw active power (ICC2) prior to entering

the standby mode, until the operation is complete.

When the device is again selected (CE = VIL), active

operations occur in accordance with the AC timing

specifications.

Automatic Sleep Mode

Advanced power management features such as the

automatic sleep mode minimize Flash device energy

consumption. This is extremely important in

battery-powered applications. The Am29LV008 auto-

matically enables the low-power, automatic sleep

mode when addresses remain stable for 200 ns. Auto-

matic sleep mode is independent of the CE, WE, and

OE control signals. Typical sleep mode current draw is

200 nA (for CMOS-compatible operation). Standard

address access timings provide new data when

addresses are changed. While in sleep mode, output

data is latched and always available to the system.

Output Disable

If the OE input is at a logic high level (VIH), output from

the device is disabled. This will cause the output pins to

be in a high impedance state.

8

Am29LV008T/Am29LV008B

Share Link: