EDS1232CABB Ver la hoja de datos (PDF) - Elpida Memory, Inc

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componentes Descripción

Fabricante

EDS1232CABB

128M bits SDRAM

Elpida Memory, Inc 

EDS1232CABB, EDS1232CATA

DC Characteristics (TA = 0 to +70°C, VDD, VDDQ = 2.5V±0.2V, VSS, VSSQ = 0V)

Parameter

/CAS latency

Symbol Grade max.

Unit

Test condition

Notes

Operating current

(CL = 2)

(CL = 3)

IDD1

IDD1

-75

105

-1A

100

-75

105

-1A

100

mA

Burst length = 1

1

tRC ≥ tRC (min.)

IO = 0mA

mA

One bank active

Standby current in power down IDD2P

1

Standby current in power down

(input signal stable)

IDD2PS

1

Standby current in non power

down

IDD2N

20

Standby current in non power

down

IDD2NS

8

(input signal stable)

Active standby current in power

down

IDD3P

5

Active standby current in power

down (input signal stable)

IDD3PS

4

Active standby current in non

power down

IDD3N

25

Active standby current in non

power down

IDD3NS

15

(input signal stable)

Burst operating current

IDD4

-75

150

-1A

130

Refresh current

IDD5

-75

210

-1A

200

Self refresh current

IDD6

2.0

Self refresh current

(L-version)

IDD6

-xxL 0.6

mA

CKE ≤ VIL (max.) tCK = 15ns

mA

CKE ≤ VIL (max.) tCK = ∞

CKE ≥ VIH (min.) tCK = 15ns

mA

CS ≥ VIH (min.)

Input signals are changed one

time during 30ns

mA

CKE ≥ VIH (min.) tCK = ∞

mA

CKE ≤ VIL (max.) tCK = 15ns

mA

CKE ≤ VIL (max.), tCK = ∞

CKE ≥ VIH (min.), tCK = 15 ns,

mA

/CS ≥ VIH (min.),

Input signals are changed one

time during 30ns.

mA

CKE ≥ VIH (min.), tCK = ∞,

mA

tCK ≥ tCK (min.),

IO = 0mA, All banks active

2

mA

tRC ≥ tRC (min.)

3

mA

VIH ≥ VDD − 0.2V,

VIL ≤ GND + 0.2V

mA

Notes: 1. IDD1 depends on output loading and cycle rates. Specified values are obtained with the output open. In

addition to this, IDD1 is measured condition that addresses are changed only one time during tCK (min.).

2. IDD4 depends on output loading and cycle rates. Specified values are obtained with the output open.

In addition to this, IDD4 is measured condition that addresses are changed only one time during tCK

(min.).

3. IDD5 is measured on condition that addresses are changed only one time during tCK (min.).

DC Characteristics 2 (TA = 0 to +70°C, VDD, VDDQ = 2.5V±0.2V, VSS, VSSQ = 0V)

Parameter

Input leakage current

Output leakage current

Output high voltage

Output low voltage

Symbol

min.

ILI

–1.0

ILO

–1.5

VOH

2.0

VOL

—

max.

1.0

1.5

—

0.4

Unit Test condition

Notes

µA

0 = VIN = VDDQ, VDDQ = VDD,

All other pins not under test = 0V

µA 0 = VIN = VDDQ DOUT is disabled

V

IOH = –1mA

V

IOL = 1mA

Preliminary Data Sheet E0247E40 (Ver. 4.0)

6

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