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CY7C1352 Datasheet PDF : 12 Pages
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CY7C1352
Burst Write Accesses
The CY7C1352 has an on-chip burst counter that allows the
user the ability to supply a single address and conduct up to
four Write operations without reasserting the address inputs.
ADV/LD must be driven LOW in order to load the initial ad-
dress, as described in the Single Write Access section above.
Cycle Description Truth Table[1, 2, 3, 4, 5, 6]
When ADV/LD is driven HIGH on the subsequent clock rise,
the chip enables (CE1, CE2, and CE3) and WE inputs are ig-
nored and the burst counter is incremented. The correct
BWS[1:0] inputs must be driven in each cycle of the burst write
in order to write the correct bytes of data.
Operation
Deselected
Suspend
Begin Read
Begin Write
Burst READ
Operation
Burst WRITE
Operation
Address
used
External
-
External
External
Internal
Internal
ADV/
CE CEN LD/
WE BWSx CLK
Comments
1
0
L
X
X
L-H
I/Os three-state following next rec-
ognized clock.
X
1
X
X
X
L-H
Clock ignored, all operations
suspended.
0
0
0
1
X L-H
Address latched.
0
0
0
0
Valid L-H
Address latched, data presented
two valid clocks later.
X
0
1
X
X
L-H
Burst Read operation. Previous
access was a Read operation. Ad-
dresses incremented internally in
conjunction with the state of
MODE.
X
0
1
X
Valid L-H
Burst Write operation. Previous
access was a Write operation. Ad-
dresses incremented internally in
conjunction with the state of
MODE. Bytes written are deter-
mined by BWS[1:0].
Interleaved Burst Sequence
First
Address
Ax+1, Ax
00
01
10
11
Second
Address
Ax+1, Ax
01
00
11
10
Third
Address
Ax+1, Ax
10
11
00
01
Fourth
Address
Ax+1, Ax
11
10
01
00
Linear Burst Sequence
First
Address
Ax+1, Ax
00
01
10
11
Second
Address
Ax+1, Ax
01
10
11
00
Third
Address
Ax+1, Ax
10
11
00
01
Fourth
Address
Ax+1, Ax
11
00
01
10
Write Cycle Descriptions[1, 2]
Read
Function
WE
BWS1
BWS0
1
X
X
Write − No bytes written
0
1
1
Write Byte 0 − (DQ[7:0] and DP0)
Write Byte 1 − (DQ[15:8] and DP1)
Write All Bytes
0
1
0
0
0
1
0
0
0
Notes:
1. X=”Don't Care”, 1=Logic HIGH, 0=Logic LOW, CE stands for ALL Chip Enables active. BWSx = 0 signifies at least one Byte Write Select is active, BWSx =
Valid signifies that the desired byte write selects are asserted, see Write Cycle Description table for details.
2. Write is defined by WE and BWS[1:0]. See Write Cycle Description table for details.
3. The DQ and DP pins are controlled by the current cycle and the OE signal.
4. CEN=1 inserts wait states.
5. Device will power-up deselected and the I/Os in a three-state condition, regardless of OE.
6. OE assumed LOW.
5
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