Q67100-Q537 Ver la hoja de datos (PDF) - Infineon Technologies

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Q67100-Q537

256 K × 4-Bit Dynamic RAM Low Power 256 K × 4-Bit Dynamic RAM

Infineon Technologies 

HYB 514256B/BL/BJ/BJL-50/-60/-70

256 K × 4-DRAM

Notes :

1) All voltages are referenced to VSS .

2) ICC1 , ICC3 , ICC4 , ICC6 and ICC7 depend on cycle rate.

3) ICC1 and ICC4 depend on output loading. Specified values are measured with the output open.

4) An initial pause of 200 µs is required after power-up followed by 8 RAS cycles before proper device operation

is achieved. In case of using internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles

instead of 8 RAS cycles are required.

5) VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Transition times are also

measured between VIH and VIL.

6) Measured with a load equivalent to 2 TTL loads and 100 pF.

7) tOFF (max.) and tOEZ (max.) define the time at which the output achieves the open-circuit conditions and is not

referenced to output voltage levels.

8) Either tRCH or tRRH must be satisfied for a read cycle.

9) These parameters are referenced to the CAS leading edge in early write cycles and to the WE leading edge

in read-modify-write cycles.

10) tWCS , tRWD , tCWD and tAWD are not restrictive operating parameters. They are included in the data sheet as

electrical characteristics only. If tWCS ≥ tWCS (min.), the cycle is an early write cycle and data out pin will remain

open circuit (high impedance) through the entire cycle; if tRWD ≥ tRWD (min.), tCWD ≥ tCWD (min.) and tAWD ≥ tAWD

(min.), the cycle is a read-modify-write cycle and I/O will contain data read from the selected cell. If neither of

the above sets of conditions is satisfied, the condition of I/O (at access time) is indeterminate.

11) Operation within the tRCD (max.) limit insures that tRAC (max.) can be met, tRCD (max.) is specified as a reference

point only. If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled by tCAC .

12) Operation within the tRAD (max.) limit insures that tRAC (max.) can be met. tRAD (max.) is specified as a reference

point only. If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled by tAA .

13) AC measurements assume tT = 5ns.

14) Either tDZC or tDZO must be satisfied.

15) Either tCDD or tODD must be satisfied.

Semiconductor Group

64

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