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PDM4M4060 Ver la hoja de datos (PDF) - Paradigm Technology

Número de pieza
componentes Descripción
Fabricante
PDM4M4060
Paradigm-Technology
Paradigm Technology Paradigm-Technology
PDM4M4060 Datasheet PDF : 10 Pages
1 2 3 4 5 6 7 8 9 10
PDM4M4060
256K x 32 CMOS
1 Static RAM Module
Features
n High-density 8 megabit Static RAM module)
n Low profile 72-lead SIMM and Angled SIMM
(Single In-line Memory Module)
n Very fast access time: 10 ns (max.)
n Surface mounted plastic components on an epoxy
laminate (FR-4) substrate
n Single 5V (±10%) power supply
n Multiple VSS pins and decoupling capacitors for
maximum noise immunity
n Inputs/outputs directly TTL compatible
Description
The PDM4M4060 is a 256K x 32 static RAM module
constructed on an epoxy laminate (FR-4) substrate
using eight 256K x 4 static RAMs in plastic SOJ pack-
ages. Availability of four chip select lines (one for
each of two RAMs) provides byte access. The
PDM4M4060 is available with access times as fast as
15 ns with minimal power consumption.
The PDM4M4060 is packaged in a 72-lead SIMM
(Single In-line Memory Module). The SIMM
2 configuration allows 72 leads to be placed on a
package 4.25” long and 0.35” wide. At only 0.650”
high, this low-profile package is ideal for systems
with minimum board spacing. The SIMM
3 configuration allows use of angled sockets to reduce
the effective module height further. The Angled
SIMM configuration allows 72 leads to be placed on a
package 4.255” long and 0.35” wide. At only 0.680”
4 high, this low-profile package is ideal for systems
with minimum board spacing.
All inputs and outputs of the PDM4M4060 are TTL
compatible and operate from a single 5V supply. Full
5 asynchronous circuitry requires no clock or refresh for
operation and provides equal access and cycle times
for ease of use.
6 Four identification pins (PD3-PD0) are provided for
applications in which different density versions of the
module are used. In this way, the target system can
read the respective levels of PD3-PD0 to determine a
256K depth.
7
Functional Block Diagram
CS1 CS2 CS3 CS4
18
ADDRESS
WE
OE
256K x 32
RAM
2
PD
8
8
8
8
I/O31-I/O0
8
9
10
11
12
Rev 2.2 - 7/17/97
8-55

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