UT8R256K1615TBDCX Ver la hoja de datos (PDF) - Aeroflex UTMC

Número de pieza

componentes Descripción

Fabricante

UT8R256K1615TBDCX

256K x 16 SRAM

Aeroflex UTMC 

Standard Products

UT8R256K16 256K x 16 SRAM

Advanced Data Sheet

October 9, 2002

FEATURES

INTRODUCTION

q 15ns maximum access time

q Asynchronous operation, functionally compatible with

industry-standard 256K x 16 SRAMs

q CMOS compatible inputs and output levels, three-state

bidirectional data bus

- I/O Voltage 2.5 to 3.3 volts, 1.8 volt core

q Radiation performance

- Intrinsic total-dose: 100K rad(Si)

The UT8R256K16 is a high-performance CMOS static RAM

organized as 262,144 words by 16 bits. Easy memory expansion

is provided by active LOW and HIGH chip enables ( E1, E2), an

active LOW output enable (G), and three-state drivers. This

device has a power-down feature that reduces power

consumption by more than 90% when deselected.

Writing to the device is accomplished by taking chip enable one

(E1) input LOW, chip enable two (E2) HIGH and write enable

- SEL Immune >100 MeV-cm2/mg

(W) input LOW. Data on the 16 I/O pins (DQ0 through DQ15)

- Onset LET > 24 MeV-cm2/mg

is then written into the location specified on the address pins

- Memory Cell Saturated Cross Section, 1.0 x 10-8cm2/bit

(A0 through A17). Reading from the device is accomplished by

- 1.0E x 10-10 errors/bit-day, Adams to 90%

taking chip enable one (E1) and output enable (G) LOW while

q

q

geosynchronous heavy ion

- Neutron Fluence: 3.0E14n/cm2

T - Dose Rate (estimated)

- Upset 1.0E9 rad(Si)/sec

N - Latchup >1.0E11 rad(Si)/sec

Packaging options:

E - TBD

Standard Microcircuit Drawing pending

M - QML compliant part

OP W

A0

L A1

E1

E2

A2

E A3

BHE

A4

V BLE

A5

A6

EA7

D A8

forcing write enable (W) and chip enable two (E2) HIGH. Under

these conditions, the contents of the memory location specified

by the address pins will appear on the I/O pins.

The 16 input/output pins (DQ0 through DQ15) are placed in a

high impedance state when the device is deselected (E1 HIGH

or E2 LOW), the outputs are disabled (G HIGH), or during a

write operation (E1 LOW, E2 HIGH and W LOW).

Pre-Charge Circuit

Memory Array

256K x 16

I/O Circuit

G

DQ(7) to DQ(0)

IN•

•

Low Byte

•

Read Circuit

A9

Data Control

Column Select

DQ(15) to DQ(8)

•

•

•

Data Control

A10 A11 A12 A13A14 A15 A16 A17

High Byte

Read Circuit

Figure 1. UT8R256K16 SRAM Block Diagram

1

Share Link: