ALD500R Ver la hoja de datos (PDF) - Advanced Linear Devices
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componentes Descripción
Fabricante
ALD500R
Advanced Linear Devices
ALD500R Datasheet PDF : 12 Pages
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DC & AC ELECTRICAL CHARACTERISTICS
TA = 25°C V supply = ±5.0V unless otherwise specified; CAZ = CREF = 0.47µf
Parameter
Supply Current
500RAU
500RA
500R
Symbol Min Typ Max Min Typ Max Min Typ Max
Unit
Test Conditions
IS
0.6 1.0
0.6 1.0
0.6 1.0 mA
V+ = 5V , A =1,B=1
Power Dissipation
PD
10
10
10
mW
V supply= ±5V
Positive Supply Range V+S
4.5
5.5 4.5
5.5
4.5
5.5 V
Note 4
Negative Supply Range V-S
-4.5
-5.5 -4.5
-5.5 -4.5
-5.5 V
Note 4
Comparator Logic 1,
Output High
Comparator Logic 0,
Output Low
Logic 1, Input High
Voltage
Logic 0, Input Low
Voltage
Logic Input Current
Comparator Delay
VOH
4
4
4
V
ISOURCE = 400µA
VOL
0.4
0.4
0.4 V
ISINK = 1.1mA
VIH
3.5
3.5
3.5
V
VIL
1
1
1V
IL
0.01
tD
1
0.01
0.01
µA
1
1
µsec Note 5
Figure 3. ALD500R TIMING DIAGRAM
1 Conversion Cycle
1.8432 MHz Clock
A INPUT
B INPUT
123,093
Clock Pulses
0.5416 µs
66.667 msec.
123,093
Clock Pulses
66.667 msec.
COUT
Positive Input Signal
NOT VALID
COUT
Negative Input Signal
NOT VALID
Auto Zero
Phase
Input Signal
Integration
Phase
START
CONVERSION
CYCLE
Clock data in
or clock data out
of counters within the
the microcontroller
or fixed logic controller,
as needed.
Fixed number
of clock pulses
by design.
START INTEGRATION CYCLE
START DEINTEGRATION CYCLE
Reference
Voltage
Deintegration
Phase
Variable
number of
clock pulses.
At VIN MAX,
max. number of
clock pulses
=~ 246,185
Integrator Zero
Phase
Auto Zero
Phase
Fixed period of
approx.1 msec.
Stop counter upon
detection of comparator
output going from high
to low state.
REPEAT
CONVERSION
CYCLE
START INTEGRATOR ZERO CYCLE
ALD500RAU/ALD500RA/ALD500R
Advanced Linear Devices
5
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