AL710 Ver la hoja de datos (PDF) - AverLogic Technologies Inc

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AL710

QUAD Video Processor

AverLogic Technologies Inc 

AL700/701/710

7.3.2 Proprietary Parallel Interface

The parallel bus interface consists of the H_WRB (latch clock), H_BUS[7:0], H_DENB

and H_RDB signals. There are internal pull-up circuits for all pins. When SP_SEL is

high, the parallel bus interface is disabled and all parallel interface pins are pulled high.

The parallel interface transfers base register address or read/write data in one H_WRB

cycle. H_WRB is a latch clock signal. H_BUS[7:0] represents an 8-bit data bus.

H_DENB defines the data bus as register address bus or data bus. The H_BUS[7:0]

appears a register address at the rising edge of H_WRB when H_DENB is High. H_RDB

defines Read/Write mode. The High H_RDB represents the host operates in the Write

mode. At the rising edge of H_WRB, read/write data is latched or read-out data is read.

The following figures show read/write timing chart of host parallel interface.

H_WRB

H_BUS(7:0)

H_DENB

H_RDB

address

ADDRESS

READ

HIZ

DATA

Figure 5: Host Read Cycle

WRITE

H_WRB

H_BUS(7:0)

address

data

don't care

data

H_DENB

ADDRESS

DATA

H_RDB

WRITE

READ

7.4 Picture Control

Figure 6: Host Write Cycle

AL700/701/710 provides various functions that can be controlled by inside registers. Picture

control takes effect on the fly. Display attributes apply to all channels but channel attributes

apply to each channel.

7.4.1 Picture Attributes

AL700/701/710 provides QUAD or FULL screen picture display. In addition, picture

location, layer priority and channel attributes can be programmed via host interface.

©2001,2002-Copyright by AverLogic Technologies, Corp. Preliminary Version C1.1 17

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