AL710 Ver la hoja de datos (PDF) - AverLogic Technologies Inc

Número de pieza

componentes Descripción

Fabricante

AL710

QUAD Video Processor

AverLogic Technologies Inc 

AL700/701/710

Pin Name

Pin Number I/O type

Description

Digital Power

VDD

8, 15, 29, 43, 53,

DP Digital power

65, 75, 101, 106,

124, 140, 156,

157, 174, 203

GND

2, 5, 26, 35, 51,

DP Digital ground

59, 71, 98, 104,

115, 131, 147,

165, 198, 206

Note: For I/O type, I, O, AP, and DP indicate input, output, analog power, and digital power

respectively.

7 Function Description

7.1 Decoder/ADC Video Input Interface

AL700/701/710 has four video input interfaces that can directly connect to external video

decoders (or video ADC outputs for AL710) and support 4 channels of 8-bit ITU-R-601/656

4:2:2 data stream. To support various video decoders, AL700/701/710 accepts different

types of sync, flags, data formats, and data sequence by adjusting data in the internal control

register #04h. The polarity of the input/output video signals can also be adjusted through

register #05h. Because all the 4 external video inputs are controlled by the same internal

control registers, using the same type of video decoders or ADC devices in the design is

recommended.

When SoftRef (register #08h<2>) is set to 0, the input active region is defined by HACTIVE

code in ITU-R-656 mode or by hardware valid pins in ITU-R-601 8-bit mode. The input

active region is defined by register CAPHSTART (#09h and #0Ah) and register

CAPVSTART (#0Bh) if SoftRef is set to 1. All the parameters are relative to the leading

edges of the input horizontal and vertical sync signals. The following diagram shows the

input active window timing and the related registers. The internal control signals are

assumed to be active High. Therefore, register POLARITY (#05h) should be adjusted to

match the required format if the input control signals are active Low.

Many video decoders support channel-multiplexing functions. AL700/701/710 supports a

channel multiplexing mode using1 decoder for 2 channels by the SW_A and SW_B output

control signals. When mux_mode (register #08h<4>) is set to 1, AL700/701/710 will control

the SW_A and SW_B output signals and automatically swap the internal decoder interface

to reflect the respective channel data. The SW_A controls the channels A and C data and

SW_B controls the channels B and D. Therefore, you should only connect the external

decoders to channels A and B interface of AL700/701/710.

©2001,2002-Copyright by AverLogic Technologies, Corp. Preliminary Version C1.1 12

Share Link: