AKD4556 Ver la hoja de datos (PDF) - Asahi Kasei Microdevices
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Fabricante
AKD4556 Datasheet PDF : 22 Pages
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ASAHI KASEI
SWITCHING CHARACTERISTICS
(Ta=-40 ∼ +85°C; VA, VD=2.4 ∼ 3.6V; CL=20pF)
Parameter
Symbol
min
typ
Master Clock Timing (MCLK)
Frequency: 128fs, 256fs, 512fs
fCLK
2.048
-
192fs, 384fs, 768fs
fCLK
3.072
-
Pulse Width Low
tCLKL 0.4/fCLK
-
Pulse Width High
tCLKH 0.4/fCLK
-
LRCK (VA, VD = 2.4V∼3.6V)
Frequency Normal Speed: 256fs, 512fs
fs
8
-
384fs, 768fs
fs
8
-
Double Speed: 256fs
fs
54
-
384fs
fs
48
-
Duty Cycle Slave mode
45
-
Master mode
-
50
LRCK (VA, VD = 2.7V∼3.6V)
Frequency Quad Speed: 128fs
fs
108
-
192fs
fs
96
-
Duty Cycle Slave mode
45
-
Master mode
-
50
Audio Interface Timing
Slave mode (VA, VD = 2.4V ∼ 2.7V)
BCLK Period: Normal Speed
tBCK
1/128fs
-
Double Speed
tBCK
1/64fs
-
BCLK Pulse Width Low
tBCKL
60
-
Pulse Width High
tBCKH
60
-
LRCK Edge to BCLK “↑”
(Note 14) tLRB
20
-
BCLK “↑” to LRCK Edge
(Note 14) tBLR
20
-
LRCK to SDTO (MSB) (Except I2S mode)
tDLR
-
-
BCLK “↓” to SDTO
tBSD
-
-
SDTI Hold Time
tSDH
20
-
SDTI Setup Time
tSDS
20
-
Slave mode (VA, VD = 2.7V ∼ 3.6V)
BCLK Period: Normal Speed
tBCK
1/128fs
-
Double / Quad Speed
tBCK
1/64fs
-
BCLK Pulse Width Low
tBCKL
33
-
Pulse Width High
tBCKH
33
-
LRCK Edge to BCLK “↑”
(Note 14) tLRB
20
-
BCLK “↑” to LRCK Edge
(Note 14) tBLR
20
-
LRCK to SDTO (MSB) (Except I2S mode)
tDLR
-
-
BCLK “↓” to SDTO
tBSD
-
-
SDTI Hold Time
tSDH
13
-
SDTI Setup Time
tSDS
13
-
Note 14. BCLK rising edge must not occur at the same time as LRCK edge.
[AK4556]
max Units
27.648
36.864
-
-
MHz
MHz
ns
ns
54
kHz
48
kHz
108
kHz
96
kHz
55
%
-
%
216
kHz
192
kHz
55
%
-
%
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
40
ns
40
ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
20
ns
20
ns
-
ns
-
ns
MS0559-E-00
- 11 -
2006/11
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