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M95128-WDL5T

256/128 Kbit Serial SPI Bus EEPROM With High Speed Clock

STMicroelectronics 

M95256, M95128

must be deselected just after the eighth bit of the

data byte has been latched in, otherwise the write

process is cancelled. As soon as the memory de-

vice is deselected, the self-timed internal write cy-

cle is initiated. While the write is in progress, the

status register may be read to check the status of

the SRWD, BP1, BP0, WEL and WIP bits. In par-

ticular, WIP contains a ‘1’ during the self-timed

write cycle, and a ‘0’ when the cycle is complete,

(at which point the write enable latch is also reset).

Page Write Operation

A maximum of 64 bytes of data can be written dur-

ing one Write time, tW, provided that they are all to

the same page (see Figure 6). The Page Write op-

eration is the same as the Byte Write operation,

except that instead of deselecting the device after

the first byte of data, up to 63 additional bytes can

be shifted in (and then the device is deselected af-

ter the last byte).

Any address of the memory can be chosen as the

first address to be written. If the address counter

reaches the end of the page (an address of the

form xxxx xx11 1111) and the clock continues, the

counter rolls over to the first address of the same

page (xxxx xx00 0000) and over-writes any previ-

ously written data.

As before, the Write cycle only starts if the S tran-

sition occurs just after the eighth bit of the last data

byte has been received, as shown in Figure 12.

DATA PROTECTION AND PROTOCOL SAFETY

To protect the data in the memory from inadvertent

corruption, the memory device only responds to

correctly formulated commands. The main securi-

ty measures can be summarised as follows:

– The WEL bit is reset at power-up.

– S must rise after the eighth clock count (or mul-

tiple thereof) in order to start a non-volatile write

cycle (in the memory array or in the status reg-

ister).

– Accesses to the memory array are ignored dur-

ing the non-volatile programming cycle, and the

programming cycle continues unaffected.

– After execution of a WREN, WRDI, or RDSR in-

struction, the chip enters a wait state, and waits

to be deselected.

– Invalid S and HOLD transitions are ignored.

POWER ON STATE

After power-on, the memory device is in the follow-

ing state:

– low power stand-by state

– deselected (after power-on, a high-to-low transi-

tion is required on the S input before any opera-

tions can be started).

– not in the hold condition

– the WEL bit is reset

– the SRWD, BP1 and BP0 bits of the status reg-

ister are un-changed from the previous power-

down (they are non-volatile bits).

INITIAL DELIVERY STATE

The device is delivered with the memory array in a

fully erased state (all data set at all “1’s” or FFh).

The status register bits are initialized to 00h, as

shown in Table 8.

Table 8. Initial Status Register Format

b7

b0

0

000

0

0

0

0

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